Tap-Sampled Delay Line Droop Detection for Processor Timing Stability
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Solution Overview
Problem
Voltage droop in processor supply voltage can lead to timing failures due to sudden changes in effective switched capacitance and clock frequency, which existing technologies struggle to rapidly and accurately detect and mitigate.
Innovation Solution
A method and apparatus using a tap sampled delay line to detect voltage droop by measuring changes in clock edge position, and reactively generating a lower-frequency processor clock signal by removing a proportion of clock pulses to mitigate droop, ensuring stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor clock frequency is suddenly increased to execute applications faster, then productivity is improved, but voltage droop occurs causing timing failures
Solution Approach 1:
The droop detection circuit performs preliminary detection of voltage droop conditions before they cause timing failures. By continuously monitoring the clock signal edge positions through the tap sampled delay line, the system identifies droop conditions in advance and can take corrective action (such as reducing clock frequency) before timing failures occur, thus maintaining reliability while allowing high productivity operation.
2Productivity
If the effective switched capacitance is suddenly increased to improve computational intensity, then productivity is improved, but voltage droop occurs causing timing failures
Solution Approach 1:
The system implements feedback by continuously monitoring the clock signal characteristics through the tap sampled delay line and using this information to detect voltage droop conditions. The detection circuit measures clock edge positions at multiple taps and compares them to identify droop, then feeds this information back to control logic that can adjust processor operation (such as reducing clock frequency or limiting capacitance changes) to prevent timing failures while maintaining high computational intensity operation.
3Use of energy by moving object
If a voltage divider configuration is used to supply voltage to the processor, then power supply efficiency is improved, but voltage droop is exacerbated due to series impedance
Solution Approach 1:
The tap sampled delay line acts as an intermediary that indirectly measures voltage droop conditions without interfering with the power supply configuration. By monitoring clock signal edge positions through the delay line taps, the system detects voltage droop caused by the voltage divider and series impedance, enabling corrective action to be taken while maintaining the efficient voltage divider power supply architecture.
Data Source
AI summary
During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.