Digital Controlled Delay Line with Glitch-Predicted Clock Alignment
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Solution Overview
Problem
Current synchronization circuits face challenges in achieving high accuracy, low latency, and efficient power usage, particularly in multi-domain applications with varying voltage and frequency requirements.
Innovation Solution
A delay balancing circuit that utilizes a digitally controlled delay line, phase detection circuitry, and glitch prediction to dynamically align clock signals across different domains, enabling dynamic voltage and frequency scaling while minimizing power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digitally controlled delay line is used to synchronize clock signals, then phase alignment accuracy is improved, but glitch conditions may occur during delay updates
Solution Approach 1:
The glitch condition prediction mechanism proactively identifies potential glitch conditions before they occur by examining the relationship between current and next delay codes and the phase difference between reference and feedback clocks. When a potential glitch is predicted, the delay code update is prevented, thereby avoiding the harmful effect before it can manifest in the output signal.
Solution Approach 2:
The patent introduces an intermediary glitch condition prediction mechanism that acts as a mediator between the delay code control and the delay line output. This intermediary layer analyzes the conditions that would lead to glitches and selectively blocks problematic updates, allowing smooth transitions only when conditions are safe, thus preventing glitches without sacrificing synchronization accuracy.
2Measurement precision
If delay code updates are performed frequently to improve synchronization accuracy, then phase alignment is improved, but latency may increase
Solution Approach 1:
The system dynamically adjusts the delay code based on real-time phase difference measurements between reference and feedback clocks. The glitch condition prediction mechanism dynamically evaluates whether updates should be performed by examining the relationship between current and next delay codes and the current phase difference, allowing the system to optimize between accuracy and latency by performing updates only when conditions are favorable.
3Use of energy by moving object
If voltage and frequency scaling are implemented to improve power efficiency, then power consumption is reduced, but clock synchronization becomes more complex
Solution Approach 1:
The delay balancing circuit serves multiple functions: it synchronizes clocks across different voltage and frequency domains, implements dynamic voltage and frequency scaling, and prevents glitches through predictive analysis. This multi-functional approach allows the system to handle power efficiency requirements without proportionally increasing complexity, as the same circuitry manages both synchronization and power management tasks.
Data Source
AI summary
A delay circuit includes a delay line including at least a first group of delay elements. The delay line is responsive to a first digital delay code to delay an input signal by a first delay value, and responsive to a change from the first digital delay code to a second digital delay code to delay the input signal by a second delay value. Control circuitry generates the first and second digital delay codes. Glitch monitoring circuitry couples to the control circuitry to conditionally gate the change from the first digital delay code to the second digital delay code based on a prediction of a glitch condition.