Single-Array Programmable Delay Line With Real-Time Calibration
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Solution Overview
Problem
Programmable delay-line circuits are affected by process, voltage, and temperature variations, leading to accuracy issues and difficulties in instantaneous delay tracking and calibration.
Innovation Solution
A programmable delay-line circuit utilizing a single ring oscillator with continuous calibration, incorporating a clock edge sampler and decoder to select an output clock signal based on sampled data outputs, and a calibration logic circuit to adjust oscillation frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a programmable delay-line circuit uses multiple delay arrays for calibration, then measurement precision is improved, but device complexity increases and mismatches between arrays cause errors
Solution Approach 1:
The patent merges the calibration function into the single delay array by using a ring oscillator that traverses the same delay elements. The calibration process uses the output of the delay array itself as a reference, eliminating the need for separate calibration arrays and reducing circuit complexity while maintaining accuracy.
Solution Approach 2:
The single delay array serves dual purposes: it functions as both the delay line for signal processing and the reference for calibration. The ring oscillator structure allows the same delay elements to be used for both measurement and calibration, eliminating mismatches between separate arrays.
2Measurement precision
If a programmable delay-line circuit uses traditional calibration methods, then delay accuracy is improved, but settling time increases and instantaneous delay tracking is hindered
Solution Approach 1:
The ring oscillator provides continuous calibration by constantly circulating through the delay array and comparing its output with the input clock signal. This continuous operation eliminates settling time and enables instantaneous delay tracking, as the calibration process occurs simultaneously with normal operation rather than requiring separate calibration phases.
Solution Approach 2:
The calibration is performed continuously in the background during normal operation, so the delay array is always calibrated and ready for instantaneous delay tracking without requiring preliminary calibration steps before use.
3Measurement precision
If a programmable delay-line circuit uses analog PLL design for calibration, then delay accuracy is improved, but adaptability to different process nodes is reduced
Solution Approach 1:
The patent replaces the analog PLL design with a digital implementation using a ring oscillator and digital logic for calibration. This substitution makes the calibration mechanism more adaptable to different process nodes, as digital circuits can be more easily scaled and adjusted across various manufacturing processes while maintaining the same fundamental calibration principle.
Data Source
AI summary
A programmable delay-line circuit is provided that includes a single ring oscillator that is calibrated continuously by a calibration logic circuit. A clock edge sampler samples an input clock responsive to a plurality of oscillator output signals from the ring oscillator to form a corresponding plurality of data output signals. A clock edge voter processes the data output signals to identify a first one of the oscillator output signals that samples an edge transition of the input clock. Based upon a desired delay, a decoder selects for a second one of the oscillator output signals to produce an output clock signal.