Shared Modulator-Demodulator Circuit Using a Delay-Line Ring Oscillator
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Solution Overview
Problem
Current transceivers require significant area and power due to separate modulation and demodulation circuits and a Phase-Locked Loop (PLL) clock source, leading to high power consumption and reduced effectiveness in low-power states, especially during channel direction reversals.
Innovation Solution
A transceiver design that integrates modulation and demodulation circuits without an external clock source, sharing common circuit elements and utilizing a single delay line as a ring oscillator, eliminating the need for a PLL and allowing for reversible channel direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate modulation and demodulation circuits with a PLL clock source are used, then the transceiver achieves reliable modulation and demodulation functions, but the area and power consumption increase significantly
Solution Approach 1:
The patent combines separate modulation and demodulation circuits into a single integrated transceiver circuit. The modulator and demodulator share common functional blocks including delay elements, multiplexers, and logic circuits, eliminating the need for separate dedicated circuits for each function. This merging reduces the overall transistor count and circuit area while maintaining both modulation and demodulation capabilities.
Solution Approach 2:
The patent implements universal functional blocks that serve multiple purposes. The delay line is used by both the modulator to generate time-encoded signals and the demodulator to measure pulse widths. The same logic circuits and control mechanisms are reused across both modulation and demodulation operations, making the circuit multi-functional and reducing redundant components.
2Reliability
If a PLL clock source is used for the modulation circuit, then the modulation function is achieved, but the power consumption and area increase
Solution Approach 1:
The patent extracts and removes the PLL clock source from the transceiver architecture. Instead of using a traditional PLL-based clock generation system, the invention employs a simplified delay-line based timing mechanism that is directly integrated into the modulation and demodulation paths. This extraction eliminates the power-hungry PLL circuit while maintaining the necessary timing and frequency control functions through the delay elements.
3Reliability
If a PLL is used as clock source, then the modulation circuit operates reliably, but the lock time is relatively long reducing effectiveness during low-power state
Solution Approach 1:
The patent removes the PLL component entirely from the system, eliminating the lock time issue. The delay-line based timing mechanism provides immediate timing reference without requiring a lock acquisition phase. When the transceiver exits low-power state, the delay elements are immediately available to establish timing relationships, avoiding the delay associated with PLL lock acquisition.
4Reliability
If separate modulation and demodulation circuits are used, then the functions are independent and reliable, but the shoreline increases
Solution Approach 1:
The patent merges separate modulation and demodulation circuits into a unified transceiver structure where both functions share the same physical circuitry. The modulator and demodulator operations are performed using the same delay elements, logic gates, and control signals, reducing the shoreline to the minimum necessary to support both functions simultaneously.
Data Source
AI summary
A transceiver, including a modulation circuit configured to modulate a first digital word into a first modulated time signal; and a demodulation circuit configured to demodulate a second modulated time signal into a second digital word, wherein the modulation and demodulation circuits are operable without an external clock source, and inseparably share one or more same circuit elements. Also, a tunable delay line may be configured to set a time rate of the modulation, wherein the modulation circuit and the demodulation circuit inseparably share the tunable delay line.