Variable Digital Delay Line Tap Testing with On-Chip Delay Matching
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Solution Overview
Problem
Modern integrated circuits with variable digital delay lines face challenges in testing due to decreasing tap delay accuracy, leading to susceptibility to communication timing errors and phase noises, especially at higher operational frequencies, making external testing methods unreliable.
Innovation Solution
A built-in testing method and device that compares the delay of taps to a configurable variable delay unit, selecting the best matching configuration, which can be transmitted over noisy lines, using a control circuit with multiplexers and a phase detector to measure timing differences and store configuration information for each tap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If external testing methods are used to evaluate delayed signals from taps, then testing can be performed outside the integrated circuit, but the testing becomes susceptible to communication timing errors and phase noises at higher operational frequencies
Solution Approach 1:
The patent introduces a control circuit as an intermediary component within the integrated circuit that directly measures tap delays by generating test signals and comparing output signals against reference signals. This internal intermediary measurement system eliminates the need for external testing connections, thereby preventing communication timing errors and phase noises from affecting the measurement reliability while maintaining ease of operation through integrated testing capability
Solution Approach 2:
The integrated circuit performs self-testing through built-in control circuits that generate test signals internally and automatically measure tap delays without requiring external testing equipment. The control circuit applies test signals to taps and evaluates the delayed output signals within the circuit itself, enabling the system to service its own testing needs while maintaining high reliability by avoiding external communication channels that introduce timing errors
2Measurement precision
If tap delay accuracy is maintained at higher operational frequencies, then the delay measurement precision improves, but the susceptibility to communication timing errors and phase noises increases
Solution Approach 1:
The control circuit acts as an internal intermediary that directly compares tap output signals with reference signals generated within the same circuit, eliminating the need for external signal transmission. This internal comparison mechanism maintains high measurement precision for tap delay accuracy while preventing communication timing errors and phase noises from degrading the measurements, as all signal paths remain within the controlled circuit environment
Solution Approach 2:
The patent extracts the measurement function from external testing equipment and relocates it within the integrated circuit itself. By taking out the vulnerable external signal transmission path and replacing it with internal signal generation and comparison, the system maintains measurement precision while eliminating the harmful effects of communication timing errors and phase noises that occur during external signal transmission
Data Source
AI summary
A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.