Delay-Locked Clock Loop With Integrated Phase Feedback
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Solution Overview
Problem
Integrated circuits (ICs) face issues with clock signal stability due to manufacturing processes and temperature variations, leading to normal operation failures.
Innovation Solution
A delay lock loop comprising a selection unit, delay unit, and phase detection unit, which adjusts the delay factor to synchronize clock signals, eliminating initial delays and reducing component count, thereby increasing usable space and reducing consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional delay lock loop is used to stabilize clock signals, then clock signal stability is improved, but device complexity increases and usable space decreases
Solution Approach 1:
The patent combines the delay unit and phase detection unit into an integrated structure where the delay unit's output is directly fed to the phase detection unit, eliminating the need for separate buffer units and reduction units. This merging reduces component count while maintaining clock signal stability through the unified feedback loop.
Solution Approach 2:
The delay unit serves multiple functions: it provides the required delay for clock signal stabilization and simultaneously feeds the phase detection unit for phase difference detection. This multi-functionality eliminates the need for separate buffer units, reducing overall device complexity while maintaining reliability.
2Reliability
If a conventional delay lock loop with multiple units is used, then clock signal stability is improved, but usable space decreases
Solution Approach 1:
By merging the delay unit and phase detection unit into a compact integrated structure and eliminating redundant buffer units and reduction units, the patent reduces the overall area occupied by the delay lock loop circuit, thereby increasing usable space on the IC chip while maintaining clock signal stability.
3Manufacturing precision
If a conventional delay lock loop with elimination unit is used, then initial delay is eliminated, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the redundant elimination unit from the conventional delay lock loop structure. The initial delay is naturally handled by the integrated delay unit's design, making separate elimination units unnecessary. This extraction reduces component count while maintaining the ability to eliminate initial delay.
Solution Approach 2:
The delay unit is designed to self-correct its initial delay through the phase detection feedback mechanism, eliminating the need for separate elimination units. The system uses its own internal feedback to automatically compensate for initial delays, reducing device complexity while maintaining manufacturing precision.
4Reliability
If more components are used in delay lock loop, then clock signal stability is improved, but consumption increases
Solution Approach 1:
By merging functional units and eliminating redundant components such as buffer units and reduction units, the patent reduces the total number of active elements in the circuit. This reduction directly lowers power consumption while maintaining clock signal stability through the optimized integrated structure.
Data Source
AI summary
A delay lock loop including a selection unit, a delay unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit is coupled to the selection unit. The delay unit includes a delay factor and delays the first clock signal to generate a third clock signal according to the delay factor. The phase detection unit is coupled to the delay unit and the selection unit and generates the indication signal according to a phase difference between the second and third clock signals. The delay unit adjusts the delay factor according to the indication signal.