Variable Delay Locked Loop for DDR Clock-DQS Phase Alignment
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Solution Overview
Problem
Existing delay locked loop circuits face challenges in maintaining accurate alignment between clock and DQS signals due to voltage fluctuations, leading to phase mismatch and data reading errors in DDR DRAM operations.
Innovation Solution
A delay locked loop circuit with a variable delay line and control circuit that adjusts delay using multiple step values based on preset conditions and phase detection modules to adaptively align rising edges, incorporating path replication and phase anomaly detection for precise timing adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional delay locked loop circuit uses fixed delay adjustment steps, then the circuit structure is simple, but the phase alignment accuracy deteriorates under voltage fluctuations
Solution Approach 1:
The patent implements dynamic delay adjustment by switching between coarse and fine adjustment modes based on phase error magnitude. The control circuit dynamically selects adjustment step sizes (first step value for coarse, second step value for fine) according to real-time phase detection results, allowing the system to adapt its complexity to the current alignment needs rather than using a fixed structure throughout.
Solution Approach 2:
The delay adjustment process is segmented into two distinct phases: coarse adjustment using a first step value to rapidly reduce large phase errors, and fine adjustment using a second step value to precisely align phases when errors are small. This segmentation allows each phase to use optimally tuned parameters for its specific task, improving overall accuracy without requiring the entire system to be overly complex.
2Reliability
If a delay locked loop circuit uses multiple delay adjustment steps with different step values, then the phase alignment accuracy improves, but the control circuit complexity increases
Solution Approach 1:
The control circuit implements dynamic adaptation by monitoring phase difference magnitude and automatically switching between coarse and fine adjustment modes. When phase error exceeds a threshold, the circuit uses the first step value for rapid correction; when within threshold, it switches to the second step value for precise alignment. This dynamic behavior improves reliability under varying voltage conditions without requiring permanently complex circuitry for all operating states.
Solution Approach 2:
The patent changes the adjustment step parameter based on the current phase error state. The control circuit modifies the delay adjustment step size from a first step value to a second step value according to whether the phase difference exceeds a preset threshold. This parameter adaptation allows the system to maintain high reliability across different voltage fluctuation scenarios while keeping the control logic manageable through clear state-based decisions.
3Measurement precision
If the delay adjustment uses a single step value, then the circuit response is fast, but the alignment precision deteriorates
Solution Approach 1:
The adjustment process is divided into two time segments: an initial coarse adjustment phase using the first step value that quickly reduces large phase errors, followed by a fine adjustment phase using the second step value that precisely achieves alignment. This temporal segmentation allows the system to spend most time in the fast coarse phase and only transition to the slower fine phase when necessary, minimizing overall adjustment time while achieving high precision.
Solution Approach 2:
The circuit dynamically transitions between two adjustment speeds based on real-time phase error feedback. When the phase difference is large, the system operates in fast coarse adjustment mode; when the phase difference becomes small (within threshold), it switches to slow fine adjustment mode. This dynamic speed adaptation ensures the system is fast when needed and precise when needed, optimizing the trade-off between adjustment time and alignment precision throughout the locking process.
Data Source
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AI summary
The present invention relates to a delay locked loop circuit, including: a variable delay line configured to delay an initial clock signal to generate a delayed clock signal; and a control circuit connected to the variable delay line, configured to control the variable delay line to perform delay adjustment of a first mode and further configured to perform delay adjustment of a second mode on the variable delay line when the delayed clock signal satisfies a preset condition.A step value of each delay adjustment of the first mode is a first step value, a step value of each delay adjustment of the second mode is a second step value, and the second step value is greater than the first step value.