Delay Locked Loop Single-Edge Synchronization Against Pulse Evaporation
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Solution Overview
Problem
Delay Locked Loops (DLLs) face challenges in locking the delay line to a stable time period, particularly when the initial delay is set to a minimum, leading to high power consumption and pulse evaporation issues due to the need to handle high-speed edges and pulses.
Innovation Solution
A method and apparatus that allow the DLL to lock from any starting delay state, including the longest delay state, by injecting only a single edge of a reference clock into the delay line, synchronizing it, and then allowing all edges to enter once lock is established, using an injector, phase detector, and synchronizer to adjust the delay line iteratively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay line starts at minimum delay setting, then the DLL can lock to the reference period, but the support circuitry must operate at much higher data rates causing increased power consumption
Solution Approach 1:
The delay line is pre-configured to start at maximum delay setting before the locking process begins. This preliminary configuration allows the support circuitry to operate at lower data rates during initialization, reducing power consumption while ensuring reliable locking when the delay is gradually adjusted to match the reference period.
Solution Approach 2:
The delay line setting is made dynamic, transitioning from maximum delay during initialization to the locked state matching the reference period. This dynamic adjustment allows the system to optimize power consumption during different operational phases while maintaining locking reliability.
2Reliability
If the delay line starts at minimum delay setting, then the DLL can lock to the reference period, but pulse evaporation occurs when the input toggles faster than the delay line can handle
Solution Approach 1:
The delay line is pre-configured to start at maximum delay setting, which is sufficiently long to prevent pulse evaporation during initialization. This preliminary configuration ensures that the input clock edges can be properly propagated and synchronized without distortion, while the delay is gradually reduced to achieve accurate locking.
Solution Approach 2:
The delay line setting dynamically transitions from maximum to the locked state, allowing the system to prevent pulse evaporation during initialization while achieving accurate locking eventually. The dynamic adjustment ensures that at no point does the delay line operate at minimum setting where pulse evaporation would occur.
Data Source
AI summary
A method and apparatus for synchronizing a delay line to a reference clock. A delay line receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control signal. An injector receives a first edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the first edge has passed through the delay line, and in response, sends the injector a second trigger to send a second edge of the clock input signal to the delay line. An edge detector compares the timing of the first edge of the delay edge signal to a timing of the first edge of the reference edge signal. A control signal is sent to the delay line to decrease or increase the delay setting of the delay line based on the comparison.