Pulse Automatic Control TRIZ Cases

A replica charge pump and difference amplifier cancel timing-mismatch error currents, reducing noise and offset in high-speed loops.

A center-swing driver and cross-coupled inverter convert low-swing CML into full-rail single-ended output with lower power and better noise rejection.

A calibration control circuit compares low- and high-temperature outputs to stabilize IC behavior without adding much area or power.

A linearizing PFD fixes the down pulse width and aligns pulse edges to cut fractional-N PLL quantization noise without extra DAC noise.

A split-gate DLL delay module cuts clock delay steps to one logic gate, improving high-frequency timing accuracy under PVT variation.

Automatic voltage-division adjustment matches coaxial impedance to suppress transmit-receive interference and preserve signal quality.

A level shift signal suppressor blocks false ON/OFF outputs from transient dV/dt noise without adding complex masking circuits or chip area.

Unequal capacitor sizing in a two-terminal M2LC cuts cell size and cost while preserving voltage control and charge balancing.

Stored capacitor voltage cancels transistor mismatch in a current mirror, improving current accuracy and stability at smaller process scales.

Parallel low- and high-frequency signal paths improve voltage translation bandwidth, speed, and low-frequency response without large passive parts.

A buffer isolates crystal shunt capacitance from the gain stage, raising negative resistance to shorten oscillator start-up time.

Selectable connection units let a memory charge pump adapt to transistor size variation, improving pumping voltage efficiency and cutting power use.

Leakage current sense resistors and a detection multiplexer estimate channel leakage, warn of integrity loss, and compensate multiplexed I/O output.

Forcing integrator output zero-crossings each clock cycle suppresses class D clipping artifacts and protects capacitors from drift.

Split gating and delaying logic gates cut DLL clock delay steps to one-gate timing, improving PVT-sensitive high-frequency accuracy.

A sleep-clock counter identifies the closest reference clock for PLL startup, cutting external pins, PCB space, and cost.

A feedback loop with capacitor hold and current generation keeps level-shifted output stable despite optical pickup and LSI supply changes.

A dual-mode crystal-less oscillator uses its accurate low-frequency mode to calibrate a less accurate high-frequency clock without external crystals.

Opposite-polarity current injection offsets threshold-induced DC shift, keeping the Miller loop linear and preserving low-pass cutoff.

Differential detectors compare set and reset lines to reject parasitic-capacitance transients and preserve accurate high-voltage gate drive control.

Measures NCO control delay and adapts PLL filter bandwidth and order to improve satellite carrier phase and frequency estimation.

Two pulse signals drive separate tri-state paths for test and normal data, cutting multiplexer delay and logic gate count at high data rates.

During high-temperature TDBI, the circuit switches to active voltage generation in standby to prevent internal voltage drop and latch-up.

A constant supply for buffer transistors and variable supply for delay transistors reduces VCO jitter and noise sensitivity in PLLs.

Shared inductors at resonant clock domain boundaries average current flow, reduce skew sensitivity, and simplify inductor sizing.

An integrated feedback loop calibrates LO duty cycle from voltage comparison, improving RF receiver linearity and noise figure under interference.

A feedback path from the high-voltage side lets the level shifter refresh differential signals and reject asynchronous common-mode noise.

A PLL limits phase slope by saturating only the proportional error term, preserving fast lock response and stable frequency tracking.

Adjustable delay units and cross-coupled blocks keep multi-phase clocks separated across process, voltage, and temperature shifts.

A pick-and-bypass bulk driver lets low-voltage transistors control high-voltage switches while limiting body diode effects and overvoltage stress.

Threshold-based switching moves a crystal oscillator from startup gain to differential operation, reducing phase noise, jitter, and relaxation modes.

An offset detection and input compensation circuit cancels amplifier offset after calibration, improving signal amplification accuracy.

A DLL locks from the maximum delay state by injecting one reference edge first, reducing power demand and avoiding pulse evaporation.

Switched-capacitor peak detection adjusts oscillator bias current to limit RF emissions, reduce jitter, and stabilize clock amplitude.

A voltage-detecting power-on control circuit enables bias-sensitive memory blocks only after both supplies are ready, avoiding unintended writes and standby current.

Coarse-fine delay tuning and interpolation generate accurate quarter-cycle clocks, improving digital clock recovery accuracy and bit error rates.

Stored replacement values pre-distort the input so a phase interpolator can correct nonlinear output behavior and reduce distortion.

Separated voltage and current feedback loops help a unidirectional output stage recover quickly from bus pull-down transients without losing regulation.

Reflected clock feedback lets on-chip DPLLs align multiple chip signals without external references, reducing layout sensitivity and sync errors.

Phase tracking and divisor updates calibrate oscillator frequency, cut test time, and improve stability against temperature drift and aging.

A digital accumulator and DDVCO replace sigma-delta fractional division to cut PLL spurs, noise, area, and power.

Multiple phase-control loops use additional feedback signals to cut PLL operating-regime setup time while preserving spectral purity.

A fractional-N PLL, SDM, and clock calibrator recover sink-side stream timing accurately and prevent buffer overflow or underflow.

Phase synchronizers let EQAM modulators run on a common system clock while aligning symbol phases to multiple source reference clocks.

A resettable flip-flop and warning gate detect failure conditions and block metastable output during clock-domain crossing.

A programmable modulo arithmetic circuit preserves multiphase PWM duty and phase ratios across frequency changes while tracking external sync signals.

Separate PMOS and NMOS bias voltages balance signal swings and rise-fall times, improving high-frequency receiver speed and gain.

Resistor biasing and common mode feedback cut 1/f noise and loop gain variation in crystal oscillators, improving phase noise with less area and power.

Comparator trip-point detectors and noise filtering improve multi-supply power-on-reset accuracy despite process and temperature variation.

Test-signal calibration tunes synthesizer gain at a coarse-tuned frequency to offset PVT variation and support stable output and higher modulation rates.

A regulated voltage and current-limited control pin lets one comparator pin handle analog hysteresis and digital latching without damage.

Digital pre-compensation in a PLL high-pass modulation path flattens frequency response and corrects oscillator non-linearity.

A lock-in actuator detects reference-signal timing and drives the loop filter or oscillator to force PLL lock within an extremely short period.

An isolation circuit forces a preset output when a powered-down voltage domain floats, preventing indeterminate level-shifter signals.

Sampled closed-loop adjustment values let a wireless subsystem correct reference frequency quickly during acquisition and source switching.

A dithered digital FLL replaces PLL-based clocking to stabilize multi-core frequencies while cutting clock power, heat, and harmonic lock risk.

A reconfigurable EPLL cascaded with an FPLL lets one line card port change link rates without interrupting other ports or dropping packets.

Training-mode delay adjustment compensates intrapair skew in differential cable receivers, cutting bit errors and supporting longer links.

A synchronization unit times phase steps within a clock phase window to avoid period irregularities and reduce PLL output jitter.

An AC-coupled tunable impetus signal matches resonant frequency to speed oscillator startup while limiting overdrive, self-cancellation, and power use.

A switch-matrix reference voltage circuit improves LCD gamma correction accuracy while bypassing excess current to protect ground-side switches.

A two-phase discharge path first drains output voltage to a reference source, then to the input source to avoid interference and cut circuit cost.