Phase Adjusting Circuit with Synchronized Steps to Minimize Jitter
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Solution Overview
Problem
Phase locked loops (PLL) with voltage controlled oscillators (VCO) experience phase jitter in clock output signals due to unintended capacitive coupling during phase step operations, leading to irregularities in clock signal generation.
Innovation Solution
An integrated phase adjusting circuit with a synchronization unit that detects and synchronizes phase step commands with the clock output signal to avoid additional phase jitter, using a control signal to execute phase steps only within a defined phase window, thereby minimizing irregularities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a phase step is executed by the interpolator unit to shift the phase of the clock signal, then the phase of the clock output signal can be adjusted, but capacitive coupling through switches causes additional shift of the following crosspoint, prolonging the extended period and shortening the following period, which results in phase jitter
Solution Approach 1:
The synchronization unit detects the phase of the clock output signal and determines the optimal timing for executing the phase step command. By performing the phase step at a specifically timed moment (when the clock signal is at a suitable phase point), the harmful capacitive coupling effects are minimized, preventing additional crosspoint shifts and period irregularities that would cause phase jitter
2Speed
If the phase step is executed without synchronization, then the phase adjustment can be performed quickly, but the unwanted coupling effect strongly depends on the relative phase, causing irregularities in clock signal periods
Solution Approach 1:
The synchronization unit continuously monitors the phase of the clock output signal and uses this feedback information to determine the appropriate timing for executing phase step commands. This closed-loop approach ensures that phase steps are synchronized with the clock signal phase, maintaining period regularity while enabling efficient phase adjustment
Data Source
AI summary
An integrated phase adjusting circuit (12) for the generation of a clock output signal (CLKout) with a phase intermediate the phases of first and second input signals of equal frequency with a fixed phase shift between said first and second signals is proposed. The circuit has an interpolator unit (30) which determines the phase of the clock signal relative to either one of the first input signal and the second input signal, and is controlled externally by a control signal (PHfine) to execute a phase step if the phase of the clock signal is to be shifted. The circuit (12) comprises a synchronization unit (40) which synchronizes the phase step with the clock output signal generated by the circuit.