Differential High-Voltage Level Shifter for Transient-Immune Gate Drive
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Solution Overview
Problem
High-voltage level translator circuits face issues with parasitic capacitance between high-voltage transistors, leading to erroneous control signals due to voltage drops caused by charging of these capacitances, which can result in misinterpretation by CMOS logic components.
Innovation Solution
A high-voltage level translator circuit employing differential detectors to monitor voltage on both set and reset control lines, filtering out transient events and ensuring reliable communication of control signals by comparing threshold voltage differences across the detectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage transistors are used to interface between logic-level input signal and high-side supply voltage, then voltage translation capability is achieved, but parasitic capacitance causes transient signals that lead to erroneous control
Solution Approach 1:
A differential detector circuit is introduced as an intermediary between the high-voltage level translator and the CMOS logic components. This detector compares the translated voltage signal with a reference voltage and only generates a control output when a valid voltage difference is detected, thereby filtering out transient signals caused by parasitic capacitance while preserving the useful voltage translation function.
Solution Approach 2:
The differential detector provides feedback by continuously monitoring the voltage difference between the translated signal and reference voltage. This feedback mechanism enables the system to distinguish between legitimate control signals and transient noise, improving reliability without sacrificing voltage translation adaptability.
2Ease of operation
If parasitic capacitance charging is allowed to occur, then high-voltage transistor switching is enabled, but voltage drops are created that are misinterpreted as control signal changes
Solution Approach 1:
The differential detector acts as an intermediary that prevents the loss of control signal information by filtering out voltage drops caused by parasitic capacitance charging. It allows transistor switching to proceed normally while discarding the spurious voltage changes that would otherwise be misinterpreted as control signals.
3Adaptability or versatility
If CMOS logic components float between input voltage and ground, then voltage level compatibility is achieved, but transient signals from parasitic capacitance are misinterpreted by the logic components
Solution Approach 1:
The differential detector serves as a mediator between the floating CMOS logic components and the high-voltage translator. It maintains voltage level compatibility while protecting the logic components from misinterpreting transient signals by only generating control outputs based on valid voltage differences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively filters out common-mode transients and ensures accurate control signal communication, even in the presence of parasitic capacitance-related transients, maintaining reliable operation of high-voltage gate drivers.
Implementation Method 1
The first differential detector has a first terminal connected to receive the level shifted Set pulse and a second terminal connected to receive the level-shifted Reset pulse, wherein the first differential detector generates a logic high output when a threshold voltage difference is present between the level-shifted Set pulse and the level-shifted Reset pulse
Implementation Method 2
A problem common to such voltage level translator circuits is the presence of parasitic capacitance between the drain and source of the high-voltage transistors used to interface between the logic-level input signal and the high-side supply voltage. The parasitic capacitances are charged by the high-side supply voltage through the associated resistors, creating a voltage drop
Data Source
AI summary
A level-shift circuit translates a control signal to a level-shifted output. The level-shift circuit includes a pulse generator circuit for providing Set and Reset pulses based on the control signal and a level-shift circuit for translating the Set and Reset pulses to level-shifted Set and Reset pulses. First and second differential detectors are connected to monitor the level-shifted Set and Reset pulses to provide detection of communicated Set and Reset pulses despite the presence of transients in the level-shift circuit. A gate drive circuit employs the Set and Reset pulses communicated by the differential detectors to generate a gate drive signal.