Sink-Side Stream Clock Recovery With PLL Calibration
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Solution Overview
Problem
Existing stream clock recovery methods in high definition multimedia digital content transport systems often fail to accurately recreate the original clock rate at the sink side due to frequency errors, leading to potential buffer overflow or underflow issues caused by bit errors and imperfect measurement mechanisms.
Innovation Solution
A stream clock recovery device is implemented with a transmitter, sink device, data extractor, calibrator, translator, phase-locked loop (PLL), and sigma-delta-modulator (SDM) to synthesize a fractional frequency and adjust for frequency deviations by calibrating the M and N values, using methods such as direct comparison and buffer filling level monitoring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional stream clock recovery methods are used, then the system is simpler, but frequency accuracy deteriorates leading to buffer overflow or underflow
Solution Approach 1:
The clock recovery process is segmented into multiple independent modules: data extractor, calibrator, translator, SDM, and PLL. Each module performs a specific function, allowing the system to achieve high frequency accuracy through coordinated operation of specialized components rather than a single complex mechanism.
Solution Approach 2:
The calibrator performs preliminary calibration of the extracted clock data before it enters the translator and PLL stages. By pre-adjusting frequency deviations and correcting errors in advance, the system achieves better overall accuracy without requiring overly complex processing in subsequent stages.
2Measurement precision
If calibration methods are added to improve frequency accuracy, then measurement precision improves, but device complexity increases
Solution Approach 1:
The calibrator implements feedback mechanisms that continuously monitor the extracted clock data and adjust calibration parameters accordingly. This feedback loop enables automatic correction of frequency deviations without requiring manual intervention or overly complex external control systems.
Solution Approach 2:
The translator module acts as an intermediary between the calibrator and the PLL, converting calibrated clock data into the appropriate format for frequency synthesis. This intermediary layer simplifies the overall system architecture by providing clear interfaces between calibration and synthesis functions.
3Measurement precision
If the sink device implements comprehensive clock recovery calibration, then frequency accuracy improves, but processing time increases
Solution Approach 1:
The calibrator performs necessary calibration operations in advance, before the clock data enters the main PLL synthesis path. By completing frequency deviation adjustments and error corrections beforehand, the system minimizes processing delays in the critical signal path while maintaining comprehensive calibration.
Solution Approach 2:
The calibration process operates continuously alongside the main clock recovery function rather than as a separate batch process. This allows the system to maintain frequency accuracy over time without periodic interruptions or extended processing delays, ensuring continuous useful action throughout operation.
Data Source
AI summary
The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.