Digital Frequency Locked Loop for Low-Jitter Multi-Core Clocking
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Solution Overview
Problem
Existing clock distribution systems in multi-core processors face challenges with power dissipation and heat management due to high-speed clock distribution, and phase locked loops (PLLs) are prone to issues like locking onto harmonics, phase noise, and jitter, necessitating a more stable and efficient method for multi-frequency clocking.
Innovation Solution
A digital frequency locked loop (FLL) system that applies dither modulation and filtering to adjust output frequencies, allowing for independent core clocking and reducing power consumption by using a low-speed reference clock to generate a high-frequency target clock, avoiding the limitations of PLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional phase locked loop (PLL) is used for clock distribution, then phase alignment between reference and output clocks can be achieved, but the system becomes susceptible to jitter, phase noise, and false locking onto harmonics
Solution Approach 1:
The patent replaces the analog PLL mechanism with a digital frequency-locked loop (FLL) that uses digital signal processing. Instead of relying on analog phase detection and voltage-controlled oscillation, the invention uses digital correlation techniques to compare the reference clock with the output clock, determining frequency and phase errors through digital computation rather than analog circuitry. This substitution eliminates the susceptibility to jitter and phase noise inherent in analog PLLs.
Solution Approach 2:
The patent implements a feedback mechanism where the digital correlation between reference and output clocks continuously monitors frequency and phase alignment. The system adjusts the output clock frequency based on the measured error signals, creating a closed-loop control system that maintains accurate synchronization without the instability problems of traditional PLLs. The feedback is performed through digital processing rather than analog loop mechanisms.
2Productivity
If a master oscillator with clock tree distribution is used, then all cores can be clocked, but power consumption and heat dissipation increase with the number of processing cores
Solution Approach 1:
The patent divides the monolithic clock distribution system into multiple independent local clock generators, each serving specific cores or core groups. Instead of one master oscillator distributing clocks to all cores through a extensive clock tree, each local generator independently produces clock signals for its designated cores. This segmentation reduces the total length of clock distribution nets and eliminates the power consumption associated with distributing high-speed clocks across the entire chip.
Solution Approach 2:
The patent enables different local clock generators to operate at different frequencies optimized for their specific core workloads. Each local generator can be independently configured to provide the appropriate clock frequency for its associated cores, allowing performance optimization without requiring a high-frequency master clock distributed to all cores. This local customization reduces overall power consumption by avoiding the need to distribute high-speed clocks to all cores uniformly.
3Speed
If PLLs are used for frequency multiplication, then high-speed local core clocking can be achieved, but the system requires continuous reference clock and is prone to capture and voltage fluctuations
Solution Approach 1:
The patent replaces the voltage-controlled oscillator (VCO) and analog phase detector of traditional PLLs with a digital correlation-based frequency synthesis approach. The system uses digital signal processing to generate the high-frequency output clock from a lower-frequency reference clock, eliminating the analog components that are susceptible to voltage fluctuations and capture effects. The digital implementation provides more stable and predictable frequency multiplication.
Solution Approach 2:
The patent introduces digital correlation processing as an intermediary between the reference clock and the output clock generation. Instead of directly using analog phase comparison, the system uses digital correlation techniques to measure the alignment between reference and output clocks, then uses this information to adjust the output frequency. This intermediary digital processing step provides more stable and noise-resistant frequency control compared to direct analog PLL mechanisms.
Data Source
AI summary
A method and systems for a digital frequency locked loop in a multi-core processor are provided. The method includes applying a dither modulation signal at a dither modulation frequency to modulate an output frequency to provide a clock signal to a core of the multi-core processor. The method further includes filtering a feedback signal of the output frequency with respect to a target frequency. The method additionally includes determining a frequency error in the filtered feedback signal as a function of alignment of the output frequency to the target frequency, and adjusting the output frequency in response to the frequency error.