DLL Delay Module Using Split Logic Gates for Finer Clock Steps
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Solution Overview
Problem
The delay step value of digital locked loops (DLLs) in prior art is less accurate, failing to meet the requirements for high-frequency circuits that demand high accuracy due to the impact of process, voltage, and temperature (PVT) variations.
Innovation Solution
A delay module comprising a first and second delay unit, each with two logic gates for inverting phase, and an inverter, where the clock signal is input through the inverter or the logic gate for gating, reducing the delay step value to the delay time of one logic gate, thereby improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay step value is reduced to improve accuracy, then the measurement precision improves, but the device complexity increases
Solution Approach 1:
The delay unit is segmented into two separate logic gates: a gating logic gate and a delaying logic gate. This segmentation allows the delay function to be divided into controllable stages, where the gating gate controls signal passage and the delaying gate provides the actual delay. By segmenting the delay unit, the patent achieves a smaller delay step value (equivalent to one logic gate delay) while maintaining circuit functionality through the coordinated operation of the two gates.
Solution Approach 2:
The patent introduces dynamic control through the gating logic gate, which can selectively enable or disable the delay path based on control signals. This dynamic mechanism allows the delay unit to be flexibly activated or deactivated, providing adaptive delay control. The gating gate receives control inputs that dynamically adjust whether the signal passes through the delaying gate, creating a controllable delay system that responds to external control signals.
2Measurement precision
If more delay units are added to reduce delay step value, then the measurement precision improves, but the device complexity increases
Solution Approach 1:
Each delay unit is segmented into two distinct logic gates with specific functions: the gating gate for control and the delaying gate for time delay. This segmentation allows the system to achieve fine-grained delay control (one logic gate delay step) without requiring multiple complete delay units. The segmented structure enables precise delay adjustment by selectively activating individual delaying gates under gate control.
Solution Approach 2:
The delay unit structure serves multiple functions: the gating logic gate provides both control functionality and signal routing, while the delaying logic gate provides both delay functionality and phase inversion. This multi-functionality reduces the need for separate dedicated components, as each logic gate performs multiple roles within the delay unit, thereby reducing overall device complexity while maintaining measurement precision.
Data Source
AI summary
A delay module, a delay method, a clock detection apparatus, and a digital locked loop (DLL) are disclosed. The delay module includes a first delay unit, a second delay unit and an inverter. Each of the first delay unit and the second delay unit include two logic gates adapted to invert a phase: a logic gate for gating and a logic gate for delaying. These two logic gates are electrically connected. The input port of the logic gate for gating of the first delay unit is electrically connected to the output port of the inverter; the output port of the logic gate for delaying of the first delay unit is electrically connected to the input port of the logic gate for delaying of the second delay unit; the input port of the inverter is electrically connected to the input port of the logic gate for gating of the second delay unit; the input port of the inverter is adapted to input a clock signal to be delayed, and the logic gate for delaying of the second delay unit is adapted to output a delayed clock signal. With the present invention, a more accurate delay step value may be achieved.