DLL Delay Module Topology for One-Gate Clock Delay Steps
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Solution Overview
Problem
The delay step value of digital locked loops (DLLs) in existing technologies is not accurate enough to meet the requirements of high-frequency circuits, leading to inefficiencies in signal processing due to variations in manufacturing techniques, voltage, and temperature.
Innovation Solution
A DLL circuit design that includes a delay module with a first and second delay unit, each comprising two logic gates for gating and delaying, and an inverter, where the clock signal is input through the inverter or the logic gate for gating, reducing the delay step value to the time of one logic gate, thereby improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay step value is reduced to improve accuracy, then the measurement precision improves, but the device complexity increases
Solution Approach 1:
The delay unit is segmented into two separate logic gates: a gating logic gate and a delaying logic gate. This segmentation allows the delay function to be divided into controllable stages, enabling the delay step value to be reduced to one logic gate time while maintaining circuit manageability through modular design.
Solution Approach 2:
The gating logic gate is controlled by a control signal that dynamically enables or disables the delay function. This dynamic control allows the circuit to adjust its operation mode, switching between different delay configurations based on the number of delay units required, thereby optimizing both accuracy and complexity management.
2Duration of action of moving object
If multiple delay units are cascaded to achieve required delay, then the delay time increases, but the delay step value accuracy decreases
Solution Approach 1:
Each delay unit is segmented into two logic gates with distinct functions. The gating logic gate provides controllable signal passage while the delaying logic gate provides precise one-unit delay. This segmentation ensures that even when multiple delay units are cascaded, each unit contributes a minimal, accurate delay step, preventing accumulation of errors.
Solution Approach 2:
The circuit incorporates a feedback mechanism where the output of each delay unit is monitored and fed back to control the gating logic gates of subsequent units. This feedback ensures that the delay chain operates coherently, maintaining synchronization and preventing phase errors that would otherwise degrade accuracy in cascaded configurations.
3Reliability
If the delay relationship is maintained under PVT variations, then the reliability improves, but the device complexity increases
Solution Approach 1:
The gating logic gates are dynamically controlled by control signals that can be adjusted in response to PVT variations. This dynamic control allows the delay units to adapt their operation, maintaining the required delay relationships between clock and data signals despite changes in process, voltage, or temperature conditions.
Solution Approach 2:
The circuit utilizes parameter changes in the logic gates themselves to compensate for PVT effects. By designing the logic gates with characteristics that are less sensitive to PVT variations, and by controlling their operation through timed enable signals, the circuit maintains stable delay relationships without requiring complex external compensation mechanisms.
Data Source
AI summary
A delay module, includes a first delay unit, a second delay unit and an inverter. Each of the first and second delay units includes: a logic gate for gating and a logic gate for delaying. The input port of the logic gate for gating of the first delay unit is electrically connected to the output port of the inverter; the output port of the logic gate for delaying of the first delay unit is electrically connected to the input port of the logic gate for delaying of the second delay unit; the input port of the inverter is electrically connected to the input port of the logic gate for gating of the second delay unit; the input port of the inverter is adapted to input a clock signal to be delayed, and the logic gate for delaying of the second delay unit is adapted to output a delayed clock signal.