Fractional-N PLL Charge Pump Linearization for Quantization Noise
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Solution Overview
Problem
Fractional-N phase-locked loops (PLLs) face significant challenges due to quantization noise injected through the phase-frequency detector and charge pump, primarily caused by the mismatch between up and down current sources, which corrupts the output clock and is difficult to mitigate with existing noise reduction techniques that introduce additional thermal and 1/f noise, switch charge injection, and component mismatch errors.
Innovation Solution
A linearizing phase frequency detector (PFD) is introduced, where the down pulse is made constant-width and the up pulse falls with the down pulse, eliminating mismatch nonlinearity, and a quantization noise reduction technique uses the down current as cancellation, with a delta-sigma modulator generating a feedback clock that reduces noise by aligning pulse edges with the VCO clock, effectively suppressing high-frequency quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a canceling digital to analog converter (DAC) is added to reduce quantization noise, then quantization noise is reduced, but thermal noise, 1/f noise, switch charge injection, and component mismatch errors are introduced
Solution Approach 1:
The patent uses the inherent down current from the charge pump (which causes nonlinearity) as the cancellation current in the DAC, converting a harmful nonlinearity into a beneficial noise-cancellation mechanism. By making the down pulse constant-width and using it for cancellation, the patent eliminates mismatch nonlinearity while reducing quantization noise, avoiding the introduction of additional thermal and 1/f noise from separate current sources
Solution Approach 2:
The down current source serves dual functions: it provides the necessary charge pump operation and simultaneously acts as the cancellation current for quantization noise reduction. This multi-functionality eliminates the need for dedicated current sources, thereby avoiding additional thermal noise, 1/f noise, and component mismatch errors that would result from separate cancellation current sources
2Measurement precision
If the feedback divider ratio is changed to maintain average VCO clock to reference clock frequency ratio, then frequency accuracy is improved, but quantization noise is generated due to feedback clock phase leading and lagging
Solution Approach 1:
The patent employs a delta-sigma modulator that uses feedback to shape and push quantization noise out of the PLL passband. The modulator continuously adjusts the feedback divider ratio while using feedback control to modulate quantization noise to high frequencies where it can be filtered, thereby maintaining frequency accuracy while reducing in-band quantization noise
Solution Approach 2:
The patent uses periodic pulse signals with fixed widths to drive the charge pump, creating regular up and down current pulses. This periodic action, combined with the constant-width down pulse, ensures linear charge delivery while the delta-sigma modulator periodically adjusts the feedback divider ratio to maintain frequency accuracy without generating excessive quantization noise
3Productivity
If the charge pump current sources are made mismatched to achieve desired charge delivery, then charge pump efficiency is improved, but nonlinearity is introduced that modulates high frequency quantization noise into the pass band
Solution Approach 1:
The patent intentionally creates asymmetry in the charge pump operation by making the down pulse constant-width while the up pulse width varies. This asymmetric design, where Idn·tp is constant and Iup·tup varies, achieves the desired charge delivery while eliminating mismatch nonlinearity. The constant-width down pulse ensures linear operation regardless of current source matching
Solution Approach 2:
The patent changes the operational parameters of the charge pump by enforcing a constant width for the down pulse (tp) while allowing the up pulse width (tup) to vary. This parameter change, combined with using the down current for DAC cancellation, achieves efficient charge delivery while maintaining linearity and eliminating the nonlinearity that would otherwise modulate quantization noise into the passband
Data Source
AI summary
Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinearity associated with up and down current source mismatch. The up pulse is made to fall when the down pulse falls, that is, when the feedback clock pulse falls.