Pulse Latch Circuit With Tri-State Mode Switching
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Solution Overview
Problem
Existing pulse latches in integrated circuits require complex multiplexers to switch between test and normal data modes, leading to increased logic gate count and data-to-output delays, which hinder high data rate operations.
Innovation Solution
A pulse generator and latch circuit design that uses two distinct pulse signals to control tri-state elements, eliminating the need for multiplexers by selectively latching test or normal data input signals based on the test enable signal, thereby reducing the data-to-output delay and logic gate count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiplexers are used to switch between test and normal data modes, then the latch can operate in both modes, but the logic gate count and data-to-output delays increase
Solution Approach 1:
The patent extracts and removes the multiplexer component from the latch circuit. Instead of using a multiplexer to switch between test and normal data modes, the invention uses separate pulse generators that directly control tri-state elements, eliminating the need for multiplexing logic and reducing gate count while maintaining dual-mode operation capability
Solution Approach 2:
The patent segments the control mechanism into separate pulse generators for test mode and normal mode operations. Each pulse generator independently controls its respective tri-state element, dividing the control function into distinct segments rather than using a single multiplexer to handle both modes, thereby reducing overall circuit complexity
2Adaptability or versatility
If multiplexers are used to switch between test and normal data modes, then the latch can operate in both modes, but the data-to-output delays increase
Solution Approach 1:
By removing the multiplexer from the data path, the patent eliminates the propagation delays introduced by multiplexer switching. The direct connection from data inputs through tri-state elements to outputs reduces the number of logic stages, thereby decreasing data-to-output delay while preserving mode switching functionality through pulse-controlled tri-state activation
3Adaptability or versatility
If complex multiplexer circuits are used, then mode switching is enabled, but the data path contains more logic gates
Solution Approach 1:
The patent extracts the multiplexer function entirely from the data path. Instead of embedding multiplexer logic within the data path, the invention uses pulse-generated control signals to activate specific tri-state elements, removing complex multiplexer circuits and reducing the number of logic gates in the critical data path while maintaining the ability to select between test and normal data modes
Data Source
AI summary
A pulse latch includes a pulse generator and a latch circuit. The pulse generator generates first and second pulse signals. The first pulse signal is generated when a test enable signal is in a first state, and the second pulse signal is generated when the test enable signal is in a second state. The latch circuit outputs the latched signal by selectively latching a normal data input signal or a test data input signal. The latch circuit includes first and second tri-state elements. The first tri-state element is controlled by the first pulse signal to enable the test data input signal to be latched when the test enable signal is in the first state. The second tri-state element is controlled by the second pulse signal to enable the normal data input signal to be latched when the test enable signal is in the second state.