Multi-Loop Frequency Synthesis for Faster PLL Lock Time

The patent divides the single phase comparison control circuit into multiple parallel control circuits (first control circuit with first phase comparator, second control circuit with second phase comparator). Each control circuit processes a different signal from the frequency conversion unit simultaneously, effectively segmenting the control function to reduce establishment time while maintaining manageable complexity through modular design.

The patent transitions from a single-dimensional control approach (one phase comparator processing one signal) to a multi-dimensional approach where multiple phase comparators process multiple signals simultaneously. This dimensional expansion in the control architecture enables parallel processing that reduces the time to establish operating regime without proportionally increasing complexity.

The patent implements dynamic control by enabling the frequency conversion unit to be controlled by multiple control voltages from different control circuits at different times. The system can dynamically switch between control circuits or combine their outputs, allowing rapid adaptation during channel changes while maintaining a structured architecture that limits complexity growth.

The patent employs multiple feedback loops where each control circuit receives feedback from the frequency conversion unit and adjusts its control voltage accordingly. This feedback mechanism in each parallel control circuit enables rapid convergence to the correct operating frequency, improving reactivity during channel changes while the feedback structure itself provides a systematic way to manage the added complexity.