Digital PLL Clock Alignment Using Reflected Signal Feedback
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Solution Overview
Problem
Existing digital phase lock loops (DPLLs) require external reference signals to align chip internal clocks, which can be cumbersome and prone to synchronization errors due to board-level layout issues, especially when synchronizing multiple chips.
Innovation Solution
Implementing DPLLs within a clock distribution block that uses point-to-point un-terminated transmission lines with half the impedance of the output clock drivers and high-threshold input buffers to achieve automatic phase alignment of clock signals across multiple chips without external references, utilizing feedback signals to synchronize clock transitions across all target chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external reference signals are used to synchronize multiple chips, then clock alignment can be achieved, but board-level layout complexity increases and synchronization reliability decreases
Solution Approach 1:
The invention extracts and eliminates the external reference signal requirement by implementing self-synchronization through feedback loops within each chip. Each chip independently generates and adjusts its clock signals using internal feedback, removing the need for external reference connections and associated board-level layout complexity.
Solution Approach 2:
Each chip performs self-synchronization by using its own clock signals as reference and adjusting its internal timing through feedback loops. The chips independently align their clocks without requiring external reference signals or complex inter-chip wiring, achieving autonomous synchronization.
2Measurement precision
If external reference signals are used for clock synchronization, then multiple chips can be aligned, but the system becomes more sensitive to layout variations and synchronization errors
Solution Approach 1:
The invention implements feedback loops within each chip that continuously monitor and adjust clock signal timing. Each chip uses feedback from its own clock outputs to maintain precise synchronization, making the system immune to external layout variations and signal integrity issues.
Solution Approach 2:
The invention introduces internal feedback signals as intermediaries that mediate the synchronization process within each chip. These feedback signals act as local references that eliminate the need for external reference signals, thereby removing sensitivity to board-level layout variations.
3Reliability
If traditional DPLL methods are used with external references, then clock synchronization is possible, but the system requires careful board-level layout to avoid uncorrectable differences
Solution Approach 1:
The invention removes the external reference signal requirement and associated board-level layout constraints by implementing self-contained feedback loops within each chip. This extraction of external dependencies simplifies manufacturing and eliminates the need for careful layout procedures.
Solution Approach 2:
Each chip independently manages its own clock synchronization through internal feedback mechanisms, eliminating the need for external reference connections and complex inter-chip wiring. This self-service approach greatly simplifies manufacturing and assembly processes.
Data Source
AI summary
This disclosure describes methods and techniques using Digital Phase Lock Loops (DPLLs) within a source chip to automatically phase align a plurality of signals at a plurality of pins on a plurality of target chips of varying distances and corresponding delays from the source chip by using each transmitted signal's reflected signal as a tuning reference. It also describes using these techniques to align signals fed back from the target chips to the source chip.