Level Shift Latch Circuit for dV/dt Error Pulse Suppression
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Solution Overview
Problem
Existing level shift circuits in semiconductor switching devices face challenges in preventing malfunctions due to voltage variations (dV/dt) and phase differences in error pulses, which require complex circuit configurations and increased IC chip size to effectively mask normal signals and error signals.
Innovation Solution
A semiconductor circuit with a level shift circuit and a latch circuit that uses a level shift signal suppressor to prevent signal generation in one output section when a signal is generated in the other, ensuring no error signals are produced even with transient voltage noise or coefficient variations, achieved through a simple configuration that maintains reliable masking without increasing IC chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the threshold value of the masking NOT circuit is reduced to fully mask the normal signal pulse width, then the capability of removing error pulses is improved, but the size of the P-MOS transistor must be increased which is limited by IC chip area constraints
Solution Approach 1:
The masking function is divided into two independent NOT circuits (first NOT circuit and second NOT circuit) instead of using a single NOT circuit with adjusted threshold. Each NOT circuit processes one of the two command signals separately, allowing independent optimization without area constraints on a single transistor size.
Solution Approach 2:
Different threshold values are applied locally to different NOT circuits based on their specific functions. The first NOT circuit uses a threshold adapted for masking the ON command signal, while the second NOT circuit uses a threshold adapted for masking the OFF command signal, optimizing error pulse removal for each signal path independently.
2Reliability
If complex circuit configurations such as comparators with different reference voltages or individual delay circuits are used to mask error pulses with phase differences, then the reliability of error pulse suppression is improved, but the device complexity and IC chip size increase
Solution Approach 1:
The masking functions for both ON and OFF command signals are merged into a single level shift circuit structure with two parallel NOT circuits, eliminating the need for separate complex masking circuits. This unified approach reduces overall device complexity while maintaining effective error pulse suppression.
Solution Approach 2:
Instead of trying to precisely align and differentiate between normal and error pulses through complex timing circuits, the invention inverts the approach by using NOT circuits to generate masking signals that actively suppress error pulses. The masking is achieved through logical inversion rather than temporal differentiation.
Data Source
AI summary
A semiconductor circuit is provided in which no error signal is generated even when the circuit is exposed to a transient voltage noise that occurs with a transition from a first state indicating a conduction of a high-potential side switching device to a second state indicating a non-conduction of the high potential side switching device, or vice versa. A high potential switching device drive circuit 1 includes short circuit devices 31 and 32 that are controlled by the second level shifted signals S6 and S7 simultaneously generated across the second load resistances 30 and 29, respectively, to thereby serving to prevent a signal from being generated at one of the output sections where the other one of the first level shifted signals S4 and S5 is to be generated, when either one of the first shifted signals S4 and S5 in level shift circuit ON and OFF sections is generated across first load resistance 28 or 27 in a level shift circuit 2.