PLL Reference Clock Detection Using Sleep Clock Frequency Estimation

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Solution Overview

Problem

Phase-locked loop (PLL) circuitry in integrated circuits has limited lockable frequency ranges, requiring additional components and increased costs to support multiple reference clock frequencies, which occupies more board space and increases electrostatic discharge risks.

Innovation Solution

A circuit and method that uses a clock counter to estimate the reference clock frequency based on a sleep clock cycle count, selecting the closest frequency from a plurality of allowed frequencies, reducing the need for external pins and associated circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If strap pins are used to encode different reference clock frequencies, then the IC can support multiple frequencies, but PCB space increases and manufacturing costs increase

Engineering Contradiction:

Improvesupport for multiple reference clock frequenciesVSAvoidPCB space

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent extracts the frequency identification function from external strap pins and relocates it to internal circuitry. The IC now determines reference clock frequency using internal oscillators and frequency detection circuits, eliminating the need for external resistor networks on strap pins, thereby reducing PCB space while maintaining multi-frequency support capability

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The IC performs self-identification of the reference clock frequency through internal frequency detection circuits that automatically measure and determine the input frequency. This self-service mechanism eliminates the need for external configuration components, reducing both PCB space and manufacturing complexity while maintaining adaptability to multiple frequencies

Inventive Principle:

Principle #25Self-service

2Adaptability or versatility

If strap pins are used to encode different reference clock frequencies, then the IC can support multiple frequencies, but on-chip real estate increases due to additional circuitry

Engineering Contradiction:

Improvesupport for multiple reference clock frequenciesVSAvoidon-chip circuitry

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the frequency detection function with the existing PLL initialization circuitry. The same internal oscillators and control logic that manage PLL operation are also used to detect and identify the reference clock frequency, eliminating the need for separate dedicated detection circuitry and reducing overall on-chip real estate

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements multi-functional circuitry that serves both PLL control and frequency identification purposes. The internal oscillators and control logic are designed to perform multiple functions: generating test signals for frequency detection and managing PLL operation, thereby reducing the need for dedicated separate circuitry and minimizing on-chip real estate requirements

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If additional external resistors are used for frequency encoding, then multiple reference clock frequencies can be supported, but manufacturing costs increase

Engineering Contradiction:

Improvesupport for multiple reference clock frequenciesVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent extracts the frequency encoding function from external passive components (resistors) and implements it using active internal circuitry. This eliminates the need for precision-matched external resistor networks, simplifying the manufacturing process and reducing component procurement and assembly costs while maintaining the ability to support multiple reference clock frequencies

Inventive Principle:

Principle #2Taking out (Extraction)

4Device complexity

If the PLL lockable frequency range is limited, then the circuit is simpler, but additional frequency multiplication/division circuitry is required to support multiple frequencies

Engineering Contradiction:

Improvecircuit simplicityVSAvoidlockable frequency range

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent applies preliminary frequency conditioning before the PLL input stage. Internal frequency multiplication or division circuits pre-adjust the reference clock frequency to fall within the PLL's narrow lockable range, enabling the simple PLL circuit to effectively support a wide range of input frequencies without requiring complex wide-range PLL design

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8089318B2Methods, algorithms, circuits, and systems for determining a reference clock frequency and/or locking a loop oscillator

Publication Date: 2012.01.03 MARVELL ASIA PTE LTD

AI summary

Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies.