Duty Cycle Calibration Circuit Using Delay-Matched Clock Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The stability of the duty cycle in duty cycle calibration circuits is compromised by external interference, affecting the accuracy of the output clock signal in wireless communication systems.
Innovation Solution
A duty cycle calibration circuit comprising a duty cycle calibration cell, delay matching cell, phase-locked loop cell, and calibration control cell, which aligns and adjusts the duty cycle of the calibration clock signal to a target value through a feedback mechanism using a feedback clock signal, overcoming variations due to process, voltage, and temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If duty cycle calibration is performed using conventional methods, then the duty cycle can be adjusted, but the stability is compromised by external interference affecting accuracy
Solution Approach 1:
The patent implements a feedback mechanism where the calibrated clock signal is fed back through a phase-locked loop to generate a feedback clock signal. This feedback signal is compared with the original clock signal to detect duty cycle deviations caused by external interference, and the calibration control signal is dynamically adjusted to compensate for these deviations, thereby maintaining both accuracy and stability
Solution Approach 2:
The patent introduces a delay matching cell as an intermediary component that generates a delayed version of the calibrated clock signal. This intermediary signal serves as a reference for comparison in the calibration control cell, enabling the system to detect and correct duty cycle variations without being directly affected by external interference
2Measurement precision
If clock multiplier technology is used to increase reference clock frequency, then phase noise performance is improved, but duty cycle stability becomes more sensitive to external interference
Solution Approach 1:
The feedback mechanism continuously monitors the duty cycle of the high-frequency clock signal generated by the clock multiplier. When external interference causes duty cycle deviations, the feedback loop detects these changes and adjusts the calibration control signal to restore the correct duty cycle, thereby maintaining stability despite the increased frequency sensitivity
3Measurement precision
If duty cycle calibration circuit is added to improve accuracy, then output accuracy is enhanced, but device complexity increases
Solution Approach 1:
The calibration control cell performs multiple functions: it generates the calibration control signal, compares clock signals, detects duty cycle deviations, and adjusts calibration parameters. By consolidating these functions into a single control cell, the patent achieves high output accuracy while minimizing the increase in overall circuit complexity
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
Provided a duty cycle calibration circuit, method and clock multiplier circuit, wherein the duty cycle calibration circuit generates a delay-matched clock signal that is aligned with the first edge of the calibration clock signal and has the same duty cycle as the calibration clock signal through a delay matching cell, and generates a feedback clock signal that is aligned with the first edge of the calibration clock signal and has the target duty cycle through a phase-locked loop cell when the phase-locked loop cell is in the locked state, thereby performing sampling processing on the delay-matched clock signal using the feedback clock signal through the calibration control cell when the phase-locked loop cell is in the locked state, can acquire a sampled signal is used to instruct the relationship between the duty cycle of the calibration clock signal and the target duty cycle, this enable the calibration control cell to generate a calibration control signal according to the sampled signal, thereby calibrating the duty cycle of the calibration clock signal to the target duty cycle, the accuracy of the generated calibration clock signal can be improved.