Delay Measurement Circuit Using Uncorrelated Signal Averaging
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Solution Overview
Problem
High precision time measurement in circuits is hindered by the manufacturing tolerance of delay elements, particularly at high speeds where traditional measurement techniques struggle with timing accuracy due to the delay approaching or dropping below the clock cycle length.
Innovation Solution
A delay measurement apparatus using a clock, clock counter, digital signal source uncorrelated with the clock, detectors, accumulators, and a calculation device to calculate the average number of clock cycles for signal transitions through the delay unit, providing accurate measurements by averaging multiple transitions and utilizing noise to reduce correlation with the clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional delay measurement techniques using clock cycle counting are used, then the measurement method is simple, but the measurement precision deteriorates when delay approaches or drops below the clock cycle length
Solution Approach 1:
The patent segments the delay measurement process into multiple discrete transition detection events. Instead of measuring a single delay period, the system divides the measurement into multiple segments (individual transitions) and accumulates timing data for each segment. This segmentation allows the system to achieve high precision by averaging multiple measurements, effectively resolving the contradiction between simple methodology and high measurement precision.
Solution Approach 2:
The patent employs periodic action by continuously detecting transitions and accumulating timing data over multiple periods. The system uses a counter to track the number of transitions and accumulators to sum the timing values, then calculates the average delay by dividing the accumulated time by the number of transitions. This periodic accumulation and averaging process enables high-precision measurement while maintaining a relatively simple measurement apparatus.
2Speed
If delay elements are reduced to minimum possible delay for high speed operation, then the circuit speed increases, but the manufacturing tolerance causes significant timing inaccuracies
Solution Approach 1:
The patent implements feedback by measuring the actual delay of each transition through the delay element and using this measured information to compensate for manufacturing variations. The measurement apparatus provides feedback data about the actual delay time, which can then be used to adjust or compensate for timing inaccuracies caused by production spread, thereby maintaining high-speed operation with improved timing accuracy.
Solution Approach 2:
The patent replaces physical mechanical adjustment mechanisms with a digital measurement and compensation system. Instead of physically adjusting delay elements to achieve precise timing, the system uses digital detection, counting, and calculation to measure and compensate for delay variations. This substitution enables high-precision timing control in high-speed circuits without requiring mechanical adjustment of the delay elements themselves.
3Loss of time
If a single transition measurement is taken, then the measurement process is fast, but the accuracy is limited to the nearest clock cycle
Solution Approach 1:
The patent maintains continuity of useful action by continuously detecting transitions and accumulating timing data without interruption. The measurement system operates continuously, with the counter and accumulators constantly updating as transitions occur. This continuous operation allows the system to rapidly accumulate multiple measurements and calculate an accurate average delay, achieving high precision while minimizing measurement time through parallel accumulation rather than sequential measurement.
Data Source
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AI summary
A delay measurement apparatus for measuring a delay unit comprising: a clock; clock counter that counts clock cycles; a digital signal source that is uncorrelated with the clock; a first detector arranged to detect transitions of the digital signal entering the delay unit; a first accumulator arranged to accumulate the current clock counter value based on the output of the first detector; a second detector arranged to detect transitions of the digital signal exiting the delay unit; a second accumulator arranged to accumulate the current clock counter value based on the output of the second detector; a measurement counter arranged to count the number of transitions of the digital signal passing through the delay unit; and a calculation device arranged to calculate an average number of clock cycles that elapse while a transition of the digital signal passes through the delay unit based on the first accumulator, the second accumulator and the measurement counter. Providing that the digital signal source is sufficiently uncorrelated with the clock, repeated measurements will result in measurements that differ by one clock cycle, i.e. a certain proportion of measurements will be N clock cycles, while the remainder will be N+1 clock cycles. Over a large number of repeated and uncorrelated measurements, the proportions of each of these measurements will be accurately reflected in the averaged output, thus providing a much more accurate measurement of the delay unit's delay.