Delay Selection Circuit for Semiconductor Memory Timing
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Solution Overview
Problem
In semiconductor memory devices with increased chip size and bank number, signal timing discordance occurs between data and command signals due to PVT variations, leading to increased tAA during read operations.
Innovation Solution
A delay selection circuit with two delay lines and a power supply voltage detection unit, along with a path selection unit, adjusts the delay amount of command signals based on PVT conditions to prevent tAA increase, and includes a storing unit to manage signal pulses during voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the chip size and number of banks are increased to enhance capacity, then the storage capacity is improved, but signal timing discordance occurs between data and command signals due to increased distance from pads
Solution Approach 1:
The patent applies local quality by providing different delay amounts to different command signals based on their specific routing distances and PVT conditions. Instead of a uniform delay approach, the system individually adjusts delays for commands like CAS, RAS, and WOW based on their specific path characteristics and operational requirements, thereby resolving timing discordance while maintaining high capacity
Solution Approach 2:
The patent implements dynamics by making the delay adjustment adaptive to changing PVT (process, voltage, temperature) conditions. The delay selection circuit dynamically modifies delay amounts based on detected PVT parameters, allowing the timing compensation to evolve with operational conditions rather than being fixed, thus maintaining signal timing precision across varying operating scenarios
2Reliability
If command signals are delayed to secure timing margin under fastest PVT conditions, then timing margin is improved, but read operation performance deteriorates due to increased tAA
Solution Approach 1:
The patent resolves this contradiction through dynamic delay adjustment based on PVT conditions. Under fastest PVT conditions, the system applies larger delay amounts to command signals to secure timing margin. Under slower PVT conditions, the delay amount is reduced or eliminated, allowing read operations to proceed at full speed. This dynamic adaptation eliminates the need to permanently sacrifice read performance for timing reliability
Solution Approach 2:
The patent changes the delay parameter adaptively based on detected PVT conditions. The delay selection circuit modifies the delay amount parameter in real-time according to process variations, voltage levels, and temperature conditions, allowing the system to optimize both timing margin and read operation speed for each specific operating scenario rather than using a fixed compromise
3Device complexity
If a fixed delay amount is applied to all command signals, then circuit complexity is reduced, but timing precision deteriorates due to inability to accommodate PVT variations
Solution Approach 1:
The patent applies segmentation by dividing the delay adjustment function into separate, independent components. Instead of a monolithic delay circuit, the system uses multiple delay line units (e.g., first delay line unit, second delay line unit) that can be independently controlled and selected. This modular approach manages complexity by organizing the delay function into manageable segments that can be individually optimized and selected based on specific command signal requirements
Solution Approach 2:
The patent uses parameter changes by detecting PVT conditions and adjusting delay parameters accordingly. The delay selection circuit monitors process, voltage, and temperature parameters, then modifies the delay amount parameter to compensate for timing variations. This parameter-based adaptation achieves high timing precision without requiring complex hardware for every possible condition, as the same circuit structure dynamically adjusts parameters in response to environmental variations
Data Source
AI summary
A delay selection circuit for use in a semiconductor memory device prevents a tAA from increasing at a read operation due to a delayed command type of signal. The delay selection circuit includes a delay line unit, a power supply voltage detection unit and a path selection unit. The delay line unit has two delay lines for delaying a command type of signal by different delay amounts. The power supply voltage detection unit detects a voltage level of a power supply voltage. The path selection unit selects one of each output of the two delay lines according to an output of the power supply voltage detection unit.