Digital Storage TRIZ Cases

Dual latches store verify status while preserving original program data for logical recovery, eliminating information loss and performance penalties.

Self-correction circuit compensates delay time of address training data to eliminate pin skew and reduce operation time.

A data transmission circuit uses a control circuit to manage processing circuit states.

Compensates for semiconductor process variations in internal resistors to maintain signal integrity without external high-precision components.

Bank groups share global input output lines via multiplexing units, reducing area occupation while maintaining data transfer efficiency.

A burst pulse generation unit and pulse shifting unit produce internal commands from read or write signals.

An adaptive reference signal adjusts resistance states to improve magnetic memory read accuracy.

Segmented bit lines and a charge transfer section maintain readout voltage margins despite increased capacitance in high-density ferroelectric arrays.

Mixed memory cell architectures store access counts in multi-transistor cells to accelerate read-modify-write cycles.

A setting information storage circuit uses multiple decoders to manage configuration data efficiently.

A memory-testing circuit allocates spare rows for defective blocks using hybrid redundancy and error-correcting code mechanisms.

A memory module uses a leakage monitoring unit to disable pull-up transistors in the on-die termination circuit.

A semiconductor current compensator stabilizes operation voltage using an operational amplifier and capacitor connected to the power output line.

A semiconductor memory device counts bank activation numbers to select high-frequency banks for targeted refresh operations.

Recovery pulses applied to adjacent cells induce local heating that reduces threshold voltages and restores unselectable cross-point memory cells.

A redefined command set enables memory devices to receive control signals reliably during timing calibration sequences.

Asymmetric switching element threshold voltages improve operation margins and reduce write error rates in memory devices.

Charge sharing circuits reduce power consumption while maintaining write capability by dynamically managing voltage levels in SRAM cells.

A semiconductor error correction circuit generates internal parity signals to delay input data during write operations.

A phase change memory device maps bit patterns to resistance states based on appearance rates.

A content addressable dynamic random-access memory enables parallel search operations by simultaneously activating sense amplifiers on shared local data lines.

A nonvolatile memory data input circuit uses multiple pipe registers and an output multiplexer to manage normal and redundancy data streams.

A memory sense operation measures threshold voltage ranges and relative positions within a single sensing event to generate error correction data.

Vertical placement of peripheral circuits above the cell array resolves integration density constraints while maintaining full device functionality.

A semiconductor device generates distinct row addresses to activate separate memory regions independently.

Precharge units adjust bit line voltages to compensate for transistor mismatch caused by process skew, ensuring reliable signal detection under PVT variations.

Vertical stacking connects adjacent arrays through extended lines, suppressing signal degradation during neural network processing.

Dual delay lines and voltage detection adjust command signals based on PVT conditions, reducing tAA during read operations.

Segmented binary and one-time programmable registers reclaim a monotonic counter after a security breach, preventing unnecessary device disposal.

A semiconductor device synchronizes data output from multiple memory regions using a comparator to compare pulse signal phases.

Polarity hold latches and blocking switches eliminate the delay of comparing functions, enhancing performance while reducing power consumption.

Hybrid dual rail memory power supply scheme isolates voltage domains using level shifters to optimize signal transfer between high and low voltage circuits.

A memory device uses test circuitry to perform processing-in-memory operations on an interface die.

A retainer node circuit captures volatile state data into resistive random access memory using nanosecond-scale write operations.

A memory circuit uses a selection circuit to supply reference values to a sense amplifier for efficient data readout.

Merges resistive NV cells into SRAM bit-cells to eliminate external mirroring arrays, reducing area usage and power consumption during power transitions.

Merging repeater functions with SRAM feedback loops reduces transistor count and power consumption while maintaining signal integrity.

Multiferroic elements enable independent memory domain writing via voltage-controlled spin torque, overcoming 65nm magnetic field scaling limits.

Partitioned content addressable memory rows use self-timed control signals to selectively enable segments based on prior match results.

Address mirroring programs dual-rank mode registers identically, reducing test time by enabling parallel rank testing.

A processing-in-memory device performs row data copy operations between word lines using a dedicated control circuit and sense amplifier.

An over-driving circuit adjusts pull-up line voltage levels to secure bit line sense amplifier sensing operations.

A word-line decoder activates specific lines in segmented memory blocks to improve cell utilization.

A two-phase boost scheme programs MRAM elements by transitioning source lines to double activation voltage during the first phase.

A single output control unit generates enable timing for DLL on and off modes using CAS latency information.