Semiconductor Memory Charge Transfer Circuit for Readout Margin
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Solution Overview
Problem
Ferroelectric memory devices face challenges in maintaining a sufficient readout margin and reducing circuit scale and current consumption, especially when integrating a large number of memory cells, due to the decrease in bit line readout voltage caused by increased bit line capacitance and reduced ferroelectric capacitor size.
Innovation Solution
A semiconductor memory device and method that utilize a first and second bit line connected via a switch, with a charge transfer section to hold and transfer readout voltages, and a comparison section to compare voltages with a reference, allowing for efficient charge transfer and voltage maintenance, thereby increasing readout voltage margin while minimizing circuit area and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to improve memory capacity, then the integration degree is improved, but the bit line capacitance increases and the readout margin decreases
Solution Approach 1:
The patent divides the bit line into two separate bit lines (first bit line and second bit line) to segment the total bit line capacitance. This segmentation allows the readout voltage to be transferred to one bit line while the other bit line can be independently controlled, effectively reducing the capacitive load on the readout path and improving the readout margin in high-capacity arrays.
2Area of moving object
If the ferroelectric capacitor size is reduced to improve integration density, then the area is reduced, but the readout voltage decreases
Solution Approach 1:
The patent introduces a charge transfer section as an intermediary mechanism between the memory cell and the bit line. This charge transfer section includes transfer transistors that actively transfer charges from the ferroelectric capacitor to the bit line, enabling small ferroelectric capacitors to generate sufficient readout voltage by controlling the charge transfer process rather than relying solely on the capacitor size.
3Device complexity
If conventional reading methods are used to maintain simplicity, then the device complexity is low, but the readout margin is insufficient in high-capacity arrays
Solution Approach 1:
The patent implements dynamic control of the reading operation by using control signals to sequentially activate different transistors in the charge transfer section. The reading operation is divided into multiple phases with different transistor configurations, allowing the circuit to adapt its structure during operation to optimize the readout margin without requiring a permanently complex circuit architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves higher readout voltage margin and reduces circuit scale and current consumption, enabling efficient data retrieval in high-capacity, low-voltage ferroelectric memory devices without the need for large negative voltage generating circuits.
Implementation Method 1
The ferroelectric memory is a nonvolatile memory in which positive and negative residual polarization (spontaneous polarization) due to hysteresis (history effect) of a ferroelectric is made to correspond to "1" and "0" of data
Implementation Method 2
a charge transfer section including: a first holding section connected to the second bit line, the first holding section being configured to hold a readout voltage from a memory section that stores data, and a second holding section connected to the first bit line, the second holding section being configured to hold a voltage generated due to transfer of charges between the first holding section and the second holding section
Data Source
AI summary
A semiconductor memory device includes: a first bit line; a second bit line connected to the first bit line via a first switch; a charge transfer section including: a first holding section connected to the second bit line, the first holding section being configured to hold a readout voltage from a memory section that stores data, and a second holding section connected to the first bit line, the second holding section being configured to hold a voltage generated due to transfer of charges between the first holding section and the second holding section, the charge transfer section being configured to transfer charges between the first holding section and the second holding section via the first bit line; and a comparison section configured to compare a voltage held in the second holding section with a reference voltage.