Semiconductor Error Correction Circuit for Data Reliability
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Solution Overview
Problem
As semiconductor devices increase operating speed, the probability of errors during data transmission also increases, necessitating a method to ensure data reliability through error correction without compromising operational efficiency.
Innovation Solution
A semiconductor device design that includes a write read control circuit and an error correction circuit, which generates and outputs internal parity signals to delay data during write and read operations, ensuring error correction and securing valid windows and strobe signal margins for reliable data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve operating speed, then productivity is improved, but the probability of errors increases which worsens reliability
Solution Approach 1:
The patent applies preliminary action by performing error correction operations in advance before data is actually read. The system calculates and stores corrected data during write operations, so when data is read, the correction has already been completed, eliminating the need to wait for correction during read operations and thus maintaining high speed while ensuring reliability
Solution Approach 2:
The patent uses an intermediary approach by introducing a separate error correction circuit that operates independently from the main data path. This correction circuit processes data through parity bits and intermediate correction stages, acting as a mediator between the high-speed data transmission and the reliability requirements
2Reliability
If error correction operations are performed to improve reliability, then data transmission reliability is improved, but the time required for data operations increases which worsens productivity
Solution Approach 1:
The core solution is to perform error correction in advance during write operations. The correction circuit calculates corrected data using parity information and stores it beforehand. During read operations, the pre-corrected data is directly output without requiring additional correction time, thus maintaining high speed while ensuring reliability
Solution Approach 2:
The patent applies skipping by bypassing the traditional sequential process where data must be read first and then corrected. Instead, the system rushes through the correction process during the write phase and skips the correction step during read phase, directly outputting the pre-corrected data to maintain high operational speed
Data Source
AI summary
A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.