Output Enable Signal Circuit for Semiconductor Memory

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Solution Overview

Problem

Conventional semiconductor memory apparatuses require large area occupancy due to separate circuits for DLL on and off modes, which reduces area efficiency and integration.

Innovation Solution

An output enable signal generating circuit that uses a single output control unit to generate signals for both DLL on and off modes by determining enable timing based on CAS latency information, reducing the need for separate circuits and minimizing area occupancy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate circuits are used for DLL on mode and DLL off mode output enable signal generation, then the reliability of data output is improved, but the area occupancy increases

Engineering Contradiction:

Improvedata output stabilityVSAvoidcircuit area occupancy

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the DLL on mode output enable signal generating circuit and DLL off mode output enable signal generating circuit into a single integrated circuit. The output enable signal output unit receives output control signals from both modes and generates the final output enable signal, eliminating the need for completely separate circuits while maintaining the reliability benefits of having dedicated control paths for each mode.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The output enable signal output unit serves multiple functions by accepting output control signals from both DLL on mode and DLL off mode, selecting the appropriate signal based on the operational mode, and generating the final output enable signal. This multi-functional unit replaces what would traditionally require separate dedicated circuits for each mode.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Area of stationary object

If a single output control unit is used for both DLL on and off modes, then the area occupancy is reduced, but the complexity of signal timing control increases

Engineering Contradiction:

Improvecircuit area occupancyVSAvoidsignal timing control complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the control functionality by providing separate output control signal generating circuits for DLL on mode and DLL off mode, each optimized for its specific timing requirements. These segmented control paths feed into a unified output enable signal output unit that handles the final signal generation, balancing area reduction with timing control complexity management.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The output enable signal output unit acts as an intermediary that receives output control signals from both DLL on mode and DLL off mode circuits. It mediates between the different timing requirements of the two modes, selecting and processing the appropriate control signal to generate the final output enable signal with correct timing for the operational mode.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8139429B2Output enable signal generating circuit and method of semiconductor memory apparatus

Publication Date: 2012.03.20 SK HYNIX INC

AI summary

An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.