Memory Module Address Mirroring for Parallel Rank Testing
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Solution Overview
Problem
High-capacity memory modules require extended test times, reducing productivity in data processing systems.
Innovation Solution
A memory module with an address mirroring function, where first and second memory chips on opposite surfaces of a printed circuit board are connected through through-via-holes or blind-via-holes, and a register programs mode registers of both ranks identically using a mode register set command, allowing for selective address mirroring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high capacity memory modules are used to meet demand for high capacity, high density, and high performance, then memory capacity is improved, but test time is extended thereby lowering productivity
Solution Approach 1:
The memory module is divided into multiple ranks with memory chips mounted on both first and second surfaces of the printed circuit board. This segmentation allows independent addressing and testing of different ranks, enabling parallel test operations that reduce overall test time while maintaining high capacity
Solution Approach 2:
The patent utilizes the third dimension by mounting memory chips on both surfaces of the printed circuit board rather than only one surface. This dual-sided configuration creates additional spatial dimensions for memory organization, allowing for more efficient test access and parallel testing operations that improve productivity without sacrificing capacity
2Quantity of substance
If high capacity memory modules are used to meet demand for high capacity, high density, and high performance, then memory capacity is improved, but test time is extended
Solution Approach 1:
The register is pre-configured with address mirroring functionality that automatically maps address signals to corresponding memory chips on opposite surfaces. This preliminary setup of address routing enables immediate parallel testing of multiple ranks without requiring sequential configuration, thereby reducing test time while maintaining high capacity
Solution Approach 2:
The patent combines multiple memory ranks into a single testable unit by implementing address mirroring that simultaneously activates corresponding chips on both surfaces of the PCB. This merging approach allows parallel testing operations to be performed on multiple memory chips at once, reducing overall test time while preserving high memory capacity
3Productivity
If address mirroring function is implemented to reduce test time, then productivity is improved, but device complexity increases due to register configuration
Solution Approach 1:
The register is designed to serve multiple functions: it acts as a standard mode register for memory chip configuration and simultaneously functions as an address mirroring controller. This multi-functionality eliminates the need for separate control logic, reducing overall device complexity while enabling productivity improvements through parallel testing
Data Source
AI summary
A memory module having an address mirroring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored.