Word-Line Decoder for Semiconductor Memory Blocks
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Solution Overview
Problem
The conventional open bit-line architecture in semiconductor memory devices results in underutilization of edge memory sections, leading to inefficient current consumption due to the need to activate multiple word lines simultaneously, which increases power usage.
Innovation Solution
The semiconductor memory device is divided into memory blocks, with a word-line decoder generating enabling signals to activate one word line for each edge memory section and one non-edge memory section concurrently, allowing for separate activation of word lines across different blocks without affecting others.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple word lines are activated simultaneously for edge memory sections, then memory cell utilization is improved, but current consumption increases
Solution Approach 1:
The memory bank is divided into multiple memory blocks (first memory block, second memory block, etc.), each with its own set of word lines. This segmentation allows independent activation of word lines in different blocks, enabling the system to activate word lines in non-edge memory sections of one block while avoiding simultaneous activation in edge memory sections, thus improving utilization without proportionally increasing current consumption.
Solution Approach 2:
Different activation strategies are applied to different memory blocks based on their characteristics. Non-edge memory sections are activated to improve utilization, while edge memory sections are managed separately to control current consumption. The word line activation is optimized locally for each block type rather than applying a uniform strategy across the entire memory bank.
2Use of energy by moving object
If one word line is activated for non-edge memory sections, then current consumption is reduced, but memory cell utilization remains suboptimal
Solution Approach 1:
By segmenting the memory bank into multiple blocks with distinct edge and non-edge memory sections, the system can selectively activate word lines in non-edge sections to improve utilization while keeping edge section activations separate, thereby achieving better overall utilization without the full penalty of activating all edge sections simultaneously.
3Device complexity
If edge memory sections are coupled with one sense amplifier array, then architecture is simplified, but memory cell utilization is halved
Solution Approach 1:
The memory bank is segmented into multiple blocks, allowing non-edge memory sections to be coupled with sense amplifier arrays while edge memory sections maintain their simplified single-array coupling. This segmentation enables the system to achieve better utilization in non-edge sections without complicating the edge section architecture.
Data Source
AI summary
A semiconductor memory device includes a memory bank of an open bit-line architecture and a word-line decoder. The memory bank is divided into a plurality of memory blocks in a bit-line direction, and each of the memory blocks includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells which are grouped into a plurality of memory sections including two edge memory sections and at least one non-edge memory section. The word-line decoder generates a plurality of word-line enabling signals based on a plurality of address signals and activates one of the word lines for each of the two edge memory sections of one of the memory blocks and one of the word lines for one of the at least one non-edge memory section of each of the other memory blocks concurrently in an active mode according to the word-line enabling signals.