Test Circuitry-Based PIM in HBM Memory Devices
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing operational latency, power consumption, and chip size while supporting processing-in-memory (PIM) functionalities, as they require additional circuitry within the memory dies that can increase size, reduce storage capacity, and introduce noise and delays.
Innovation Solution
The implementation of test circuitry-based PIM in High Bandwidth Memory (HBM) devices, which utilizes existing circuitry for test functions to perform PIM operations, reduces overhead by locating PIM circuitry outside the memory dies, such as on an interface die, thereby minimizing the impact on memory die size and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional PIM circuitry is integrated within the memory dies, then processing-in-memory functionality is enabled, but memory die size increases and storage capacity is reduced
Solution Approach 1:
The patent extracts PIM circuitry from the memory die and relocates it to a separate interface die. This extraction removes the harmful effect of PIM circuitry occupying valuable memory die area, allowing the memory die to maintain its full storage capacity while still enabling PIM functionality through the external interface die.
Solution Approach 2:
The patent segments the memory device into distinct functional components: memory dies for storage and an interface die for PIM operations. This segmentation separates the PIM functionality from the storage functionality, allowing each component to be optimized independently without compromising the other.
2Adaptability or versatility
If additional PIM circuitry is integrated within the memory dies, then processing-in-memory functionality is enabled, but manufacturing complexity increases
Solution Approach 1:
By extracting PIM circuitry from the memory die, the patent simplifies the memory die design and manufacturing process. The interface die, which is already present in HBM architectures for control and data transfer, is enhanced with PIM functionality, avoiding the need to modify complex memory die fabrication processes.
3Productivity
If PIM operations are performed using conventional memory access pathways, then processing capability is achieved, but operational latency and power consumption increase
Solution Approach 1:
The patent merges PIM circuitry with the existing interface die that already manages high-speed data transfer between memory stacks. This merging allows PIM operations to utilize the existing high-bandwidth communication pathways and control logic, achieving low-latency processing without requiring separate data transfer paths.
Solution Approach 2:
The interface die acts as an intermediary between the memory dies and the host system, performing PIM operations on data while it resides in the memory stack. This intermediary approach enables processing to occur at the point of data storage, eliminating the need to transfer data to external processors and reducing operational latency.
4Area of stationary object
If PIM circuitry is located on the interface die rather than memory die, then memory die size and performance are maintained, but additional inter-die communication overhead is introduced
Solution Approach 1:
The patent combines PIM control logic with the existing interface die that already handles all communication with memory dies. This combination means that PIM operations utilize the same communication infrastructure already present for memory control, avoiding the need for additional dedicated communication pathways and minimizing inter-die communication overhead.
Data Source
AI summary
Disclosed are methods, systems, and apparatuses for a memory device with test circuitry-based processing-in-memory (PIM). The memory device utilizes circuitry used to control, sequence, and/or perform test functions, found on a die of the memory device (e.g., an interface die and/or memory die), to perform PIM functions. For example, the memory device may utilize a memory built-in self-test (mBIST) automatic pattern generator (APG) for PIM sequencing. To control PIM operations, the mBIST APG may fetch and decode microcode instructions local to the die. The microcode instructions may be fetched from a read-only memory (ROM) and/or non-volatile memory. Microcode instructions to perform desired PIM operations may be written to the non-volatile memory by a host device coupled to the memory device.