Nonvolatile Memory Data Input Circuit Speed Enhancement
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Solution Overview
Problem
Conventional nonvolatile memory devices have limited data input speed due to the storage speed of a pipe latch, which is coupled to a global data line, restricting the sequential storage and processing of normal and redundancy data.
Innovation Solution
A data input circuit with multiple pipe registers coupled to a global data line, configured to sequentially latch data in response to latch signals, and an output multiplexer to selectively output the latched data, allowing for increased data input speed by managing normal and redundancy data separately through redundancy and global data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single pipe latch is coupled to a global data line for data storage, then the circuit structure is simple, but the data input speed is limited
Solution Approach 1:
The patent divides the data storage function into multiple pipe registers (first pipe register, second pipe register, etc.) instead of using a single pipe latch. Each pipe register is coupled to the global data line and can independently latch data in response to latch signals, enabling parallel data processing and increasing data input speed while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The multiple pipe registers are configured to perform the same data latching function but can operate simultaneously on different data bits or words. The output multiplexer then selectively outputs data from any of the pipe registers based on control signals, providing multi-functionality that increases data throughput without requiring completely separate data paths
2Productivity
If data are sequentially stored in a pipe latch, then the circuit is easy to control, but the storage speed cannot match the reception speed of normal and redundancy data
Solution Approach 1:
The pipe registers are pre-configured and ready to latch data immediately when latch signals are applied. Instead of sequentially processing data through a single latch, multiple pipe registers are prepared in advance to simultaneously capture different portions of the incoming data stream, enabling the storage speed to keep pace with the data reception speed from the global data line
Solution Approach 2:
The system uses periodic latch signals to control the pipe registers, where each pipe register is activated at different time intervals or in different sequences. This periodic control mechanism allows multiple registers to be efficiently utilized for storing normal data and redundancy data at high speeds while maintaining systematic and manageable control logic
3Speed
If one pipe register is used for data latching, then the data path is simple, but the sequential output capability is limited
Solution Approach 1:
The output multiplexer dynamically selects which pipe register's data to output based on control signals. This dynamic switching capability allows the system to flexibly route data from any of the multiple pipe registers to the output in sequence, enabling high-speed data output while adapting to different data processing requirements without requiring a fixed, complex data path structure
Data Source
AI summary
The data input circuit of a nonvolatile memory device includes a redundancy multiplexer configured to selectively output normal data and redundancy data to an internal global data line in response to a redundancy signal, a plurality of pipe registers coupled to the internal global data line and configured to latch normal data or redundancy data received through the internal global data line in response to a plurality of respective latch signals, and an output multiplexer configured to sequentially output the latched data in response to a plurality of selection signals.