Semiconductor Device Peripheral Circuit Integration
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Solution Overview
Problem
Current semiconductor devices with vertical channel transistors face challenges in integrating memory cells and peripheral circuit patterns effectively, leading to reduced integration density and efficiency.
Innovation Solution
The semiconductor device incorporates a bit line sense amplifier (BLSA) circuit pattern and a column circuit pattern on a substrate, with a cell array featuring bit lines, gate electrodes, gate insulation patterns, channels, and capacitors, arranged in a specific layout to increase integration density by optimizing the placement of peripheral circuit patterns in empty spaces adjacent to the BLSA circuit pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cells and peripheral circuit patterns are integrated on the same substrate, then device functionality is improved, but integration density decreases due to space constraints
Solution Approach 1:
The peripheral circuit patterns are positioned in the third direction (vertical direction) overlapping the cell array, rather than only in the first direction (horizontal plane). This three-dimensional arrangement allows peripheral circuits to occupy vertical space above the memory cells, effectively increasing integration density while maintaining full device functionality.
2Area of stationary object
If peripheral circuit patterns are placed in empty spaces adjacent to BLSA circuit pattern, then space utilization is improved, but circuit complexity increases
Solution Approach 1:
The substrate is divided into distinct regions: a first region containing the BLSA circuit pattern and adjacent empty spaces, and a second region containing the cell array. Peripheral circuit patterns are strategically placed in the empty spaces of the first region, segmenting the layout to maximize space utilization while maintaining clear functional separation that manages circuit complexity.
Data Source
AI summary
A semiconductor device includes a BLSA circuit pattern on a substrate, a column circuit pattern on a portion of the substrate adjacent to the BLSA pattern, and a cell array. The cell array includes bit lines extending in a first direction and spaced apart from each other in a second direction on the BLSA circuit pattern and the column circuit pattern, gate electrodes extending in the second direction and spaced apart from each other in the first direction, a gate insulation pattern on a sidewall in the first direction of the gate electrode, a channel on a sidewall in the first direction of the gate insulation pattern and contacting the bit line, a landing pad on the channel, and a capacitor on the landing pad. The BLSA circuit pattern and the column circuit pattern overlap the cell array in a vertical direction.