Semiconductor Device Row Address Generation for Parallel Testing
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Solution Overview
Problem
The increasing complexity of semiconductor devices, such as DRAM, leads to higher cell failure probabilities, making accurate testing challenging and time-consuming, which affects the reliability and production efficiency of semiconductor chips.
Innovation Solution
A semiconductor device design that divides the memory region into multiple regions, generates multiple row addresses, and employs a compression circuit to perform a compressive test, reducing test time by activating and testing each region independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of cells integrated in a single semiconductor chip increases, then the functionality and capacity of the device is improved, but the probability of cell failures increases and testing becomes more difficult
Solution Approach 1:
The patent divides the memory region into multiple regions (first region and second region) and activates them independently using different row addresses. This segmentation allows parallel testing of multiple regions simultaneously, improving testing efficiency and reliability without being constrained by the total number of cells in the device.
2Measurement precision
If a comprehensive test of all cells is performed to ensure reliability, then the accuracy of failure detection is improved, but the test time increases significantly
Solution Approach 1:
By dividing the memory into multiple independently testable regions and activating them in parallel through different row addresses, the patent achieves comprehensive coverage of all cells while reducing total test time. The segmentation enables simultaneous testing rather than sequential testing of all cells.
Solution Approach 2:
The patent prepares multiple row addresses in advance that can activate different regions of the memory. This preliminary preparation of address sequences allows the testing system to quickly switch between regions and perform parallel testing without time-consuming reconfiguration during the actual test execution.
3Productivity
If parallel test is implemented by enabling all banks and allocating one test pin per bank, then the test speed is improved, but the device complexity and resource requirements increase
Solution Approach 1:
The patent makes the existing row address generation circuit and memory structure serve dual purposes: normal operation mode and parallel test mode. By selectively activating different regions through row addresses, the same hardware infrastructure performs both regular memory operations and comprehensive parallel testing, eliminating the need for dedicated test hardware and reducing overall system complexity.
Data Source
AI summary
A semiconductor device includes a row address generation circuit, a first region, and a second region. The row address generation circuit is configured to generate a first row address from an active signal and a first bank address and configured to generate a second row address from the active signal and a second bank address. The first region is activated by the first row address and an internal address. The second region is activated by the second row address and the internal address. One of the first and second bank addresses is selectively generated according to a command/address signal.