Integrated SRAM with Non-Volatile Resistive Mirror Cells
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Solution Overview
Problem
Existing SRAM technologies require a separate non-volatile memory array for data mirroring, which increases area usage and power consumption due to the need to read and rewrite data during power-down and power-up events, and involves additional circuitry and bus transactions.
Innovation Solution
Integration of non-volatile mirror cells within each SRAM bit-cell, allowing for self-storing and self-restoring of data without external NV memory, using resistive NV memory elements that change resistance states to store data, reducing the need for external data transfer and minimizing additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate non-volatile memory array is used to mirror the SRAM, then data can be saved during power-down, but the area usage increases
Solution Approach 1:
The patent merges the non-volatile memory functionality directly into the SRAM bit-cell structure by integrating resistive memory elements (such as MRAM or ReRAM cells) with the volatile SRAM storage nodes. This integration allows the same physical structure to provide both volatile high-speed storage and non-volatile data retention, eliminating the need for a separate NV memory array and thus reducing area usage while maintaining data retention capability.
Solution Approach 2:
The integrated resistive memory elements serve multiple functions: they act as non-volatile storage elements that retain data during power-down, and simultaneously function as part of the SRAM bit-cell structure during normal operation. This multi-functionality allows a single structure to replace what would traditionally require separate components, resolving the area contradiction.
2Reliability
If a separate non-volatile memory array is used to mirror the SRAM, then data can be saved during power-down, but power consumption increases due to read and rewrite operations
Solution Approach 1:
By merging the NV memory functionality into the SRAM bit-cell, the patent eliminates the need for separate read and write operations between distinct SRAM and NV memory arrays. The integrated structure allows data to be naturally retained in the resistive memory elements during power-down without active reading, and automatically restored during power-up without extensive rewriting, thus reducing power consumption.
Solution Approach 2:
The integrated resistive memory elements automatically retain data during power-down without requiring active management or frequent read/write operations. The non-volatile nature of the resistive memory provides self-service data retention, eliminating the need for continuous power or frequent data copying operations that would consume energy.
3Reliability
If a separate non-volatile memory array is used to mirror the SRAM, then data can be saved, but additional circuitry and bus transactions are required
Solution Approach 1:
The patent combines the NV memory functionality directly into the SRAM bit-cell structure, eliminating the need for separate data transfer buses and complex control circuitry. The integrated structure allows data to be stored and retrieved within the same physical location, removing the need for external NV memory interfaces and data path infrastructure.
Solution Approach 2:
The patent extracts the NV memory functionality from a separate external array and embeds it directly within the SRAM bit-cell structure. This extraction and integration removes the need for complex external connections, bus transactions, and separate control logic, simplifying the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and area usage by eliminating the need for external NV devices, achieving higher layout efficiency and automatic data restoration with minimal overhead, while maintaining SRAM performance.
Implementation Method 1
using resistive NV memory elements that change resistance states to store data
Data Source
AI summary
An apparatus is provided which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements. A method is provided which comprises performing a self-storing operation, when a voltage applied to a SRAM cell decreases to a threshold voltage, to store voltage states of the SRAM cell to at least two NV resistive memory elements, wherein the at least two NV resistive memory elements are integrated with the SRAM cell; and performing self-restoring operation, when the voltage applied to the SRAM cell increases to the threshold voltage, by copying data from the at least two NV resistive memory elements to storage nodes of the SRAM cell.