Semiconductor Device Synchronization Using Pulse Phase Comparison
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Solution Overview
Problem
There is a need for semiconductor devices that can operate at higher speeds to accommodate increasing demands for performance in semiconductor systems, as existing Single Data Rate (SDR) synchronous devices are limited in speed compared to Double Data Rate (DDR) devices.
Innovation Solution
A semiconductor device is designed with a comparator and data output unit that synchronizes data output from multiple memory regions using strobe signals, allowing for efficient data transfer by comparing pulse signals and generating detection signals to define pulse widths for output strobe signals, thereby enabling synchronization and increased operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SDR synchronous semiconductor devices are used to improve operation speed, then the device can operate in synchronization with external clock signals, but the operation speed is limited compared to DDR devices
Solution Approach 1:
The semiconductor device is divided into multiple memory regions (first memory region and second memory region), each capable of independent data output. This segmentation allows parallel data transmission channels, effectively doubling the data transfer rate while maintaining SDR architecture, thus resolving the contradiction between operation speed and productivity
Solution Approach 2:
Multiple memory regions are merged into a single semiconductor device with unified control logic. The comparator and data output unit coordinate multiple memory regions to output data simultaneously, combining their capabilities to achieve DDR-level productivity while maintaining SDR's operational simplicity
2Productivity
If multiple memory regions are added to increase data output capacity, then productivity improves, but device complexity increases
Solution Approach 1:
The comparator and data output unit are designed as universal control components that manage multiple memory regions through a unified mechanism. This multi-functional design allows the same control logic to coordinate different memory regions, increasing data output capacity without proportionally increasing device complexity
Solution Approach 2:
The comparator performs preliminary phase comparison of pulse signals from different memory regions before data output. This preliminary action ensures synchronized data transmission is established in advance, allowing multiple memory regions to operate协调ly without requiring complex real-time coordination mechanisms
Data Source
AI summary
The semiconductor device includes a comparator and a data output unit. The comparator compares a phase of a first pulse signal generated in a first memory region with a phase of a second pulse signal generated in a second memory region and responsively generates a detection signal. The data output unit outputs first data received from the first memory region as output data in synchronization with a first output strobe signal generated by defining a pulse width of a first strobe signal in response to the detection signal and outputs second data received from the second memory region as the output data in synchronization with a second output strobe signal generated by defining a pulse width of a second strobe signal in response to the detection signal.