Memory Testing Circuit Hybrid ECC Redundancy Repair
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Solution Overview
Problem
Current memory testing and repair techniques face challenges in combining conventional memory repair with error-correcting code (ECC) methods, leading to inefficiencies and test escapes, particularly in high-density semiconductors like MRAM, where soft errors and fabrication faults are prevalent.
Innovation Solution
A memory-testing circuit that disables ECC circuitry during testing, performs pre- and post-repair operations by allocating spare rows or columns based on error bit counts, and classifies memory as non-repairable, repair-needed, or error-free, using a combination of redundancy and ECC to avoid test escapes and optimize repair processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row and column repair techniques are used alone, then manufacturing yield is improved, but the ability to handle soft errors and fabrication faults is insufficient
Solution Approach 1:
The patent combines conventional redundancy-based repair techniques with ECC-based repair techniques into a unified hybrid repair system. The memory device includes both spare rows/columns for conventional repair and ECC circuitry for error correction, allowing the system to handle both fabrication faults (via redundancy) and soft errors (via ECC), thereby improving both manufacturing yield and error handling capability simultaneously
2Measurement precision
If ECC circuitry is enabled during testing, then soft error detection is improved, but test escapes occur due to interaction between ECC and repair circuitry
Solution Approach 1:
The patent applies preliminary action by performing conventional redundancy-based repair before enabling ECC for soft error detection. During the repair phase, ECC is temporarily disabled or bypassed to avoid interference, allowing accurate detection of fabrication faults. After repair, ECC is enabled to detect and correct soft errors, ensuring both repair accuracy and soft error detection capability without test escapes
3Reliability
If multiple repair operations are performed sequentially, then repair completeness is improved, but test time increases
Solution Approach 1:
The patent merges conventional repair operations with ECC operations into a coordinated hybrid repair process. Instead of performing separate sequential repairs, the system integrates both repair mechanisms to work together efficiently. The control logic coordinates redundancy-based repair and ECC-based repair in a unified flow, reducing redundant testing and minimizing total test time while ensuring both fabrication faults and soft errors are handled
Solution Approach 2:
The patent applies partial action by selectively applying different repair strategies based on the type of defect detected. For fabrication faults, conventional redundancy repair is applied; for soft errors, ECC correction is applied. This selective approach avoids performing unnecessary repair operations, reducing test time while maintaining repair completeness for the specific defect types present
Data Source
AI summary
A memory-testing circuit configured to perform a test of a memory comprising error-correcting code circuitry comprises repair circuitry configured to allocate a spare row or row block in the memory for a defective row or row block in the memory, a defective row or row block being a row or row block in which a memory word has a number of error bits greater than a preset number, wherein the test of the memory comprises: disabling the error-correcting code circuitry, performing a pre-repair operation, the pre-repair operation comprising: determining whether the memory has one or more defective rows or row blocks, and allocating one or more spare rows or row blocks for the one or more defective rows or row blocks if the one or more spare rows or row blocks are available, and performing a post-repair operation on the repaired memory.