Processing-in-memory device row data copy control circuit
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Solution Overview
Problem
The existing hardware systems with separate memory and processor units face limitations in data communication, hindering the performance improvement of artificial intelligence hardware due to increased operational requirements for deep learning applications, which necessitate efficient data transfer between memory and processing units.
Innovation Solution
A processing-in-memory (PIM) device is designed with integrated operating circuits and memory circuits, featuring a memory cell array, sense amplifier circuits, and a control circuit that performs row data copy operations between sub-memory cell arrays using control signals, enabling efficient data transfer and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate memory and processor units are used, then device complexity is reduced and ease of manufacture is improved, but data communication efficiency deteriorates and productivity decreases
Solution Approach 1:
The patent merges memory circuits and operating circuits into a single integrated structure where memory cells are directly coupled with sense amplifier circuits and control circuits on the same semiconductor chip. This integration eliminates external data communication interfaces, enabling high-speed data transfer while maintaining manageable device complexity through unified architecture design.
Solution Approach 2:
The integrated memory device performs multiple functions within a single chip: data storage in memory cells, data sensing and amplification through sense amplifier circuits, and data control through control circuits. This multi-functionality enables both high-speed data transfer and complex operations without requiring separate processor units, resolving the contradiction between productivity and device complexity.
2Productivity
If deep learning operations are increased to improve AI performance, then computational capability is improved, but data communication requirements increase and bottleneck the performance improvement
Solution Approach 1:
By integrating memory and operating circuits, the patent eliminates the time-consuming data transfer between separate memory and processor units. The control circuit can directly access and manipulate data in memory cells through the sense amplifier circuit, enabling rapid execution of deep learning operations without communication bottlenecks.
Solution Approach 2:
The integrated architecture enables continuous data access and processing operations within the memory device itself. The control circuit can sequentially perform operations on multiple word lines without interrupting the data flow, maintaining continuous computational action that is essential for high-performance deep learning applications.
3Measurement precision
If sequential row operations are performed to copy data between word lines, then data transfer precision is improved, but operation time increases
Solution Approach 1:
The control circuit performs preliminary activation of the sense amplifier circuit before data transfer operations. This preliminary action prepares the data path in advance, enabling rapid and accurate sequential row operations without excessive delay, thus balancing data transfer precision with acceptable operation time.
Data Source
AI summary
A processing-in-memory device includes a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, a sense amplifier circuit coupled to the plurality of bit lines, and a control circuit configured to perform a row data copy operation that copies data of a first word line to a second word line, among the plurality of word lines. The control circuit is configured to sequentially perform operations according to an active control signal, a row close control signal, and a row open control signal to perform the row data copy operation.