Node Retainer Circuit Using RRAM for State Preservation
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Solution Overview
Problem
Current memory technologies face challenges in quickly and efficiently retaining state information during power-down and restoring it upon power-up, particularly in volatile multi-state components, due to limitations in write and read times and power consumption.
Innovation Solution
A retainer node circuit utilizing a non-volatile resistive-switching memory cell that writes state information to a resistive random access memory (RRAM) in under 50 nanoseconds and reads it back in a similar timeframe, enabling rapid power-cycling and significant power savings by disconnecting volatile multi-state elements during sleep mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile multi-state components are used for state retention, then fast switching speed is achieved, but power consumption increases and state loss occurs during power-down
Solution Approach 1:
The patent applies preliminary action by writing state information to non-volatile RRAM memory before power-down occurs. The retainer node circuit captures the state from volatile multi-state components and stores it in RRAM in advance, ensuring state preservation without continuous power consumption during sleep mode.
Solution Approach 2:
The retainer node circuit acts as an intermediary between volatile multi-state components and non-volatile RRAM memory. It facilitates rapid state transfer during power-down and power-up, enabling the system to maintain fast switching characteristics while utilizing the power-saving benefits of non-volatile memory.
2Use of energy by moving object
If non-volatile memory is used for state retention, then power consumption decreases during sleep mode, but write and read times increase
Solution Approach 1:
The circuit performs preliminary state capture and validation before writing to RRAM. By preparing the state information in advance and using a dedicated retainer node circuit, the write operation is optimized to complete in under 50 nanoseconds, minimizing the time penalty of non-volatile memory storage.
3Use of energy by moving object
If state information is written to RRAM during power-down, then state retention is achieved with minimal power consumption, but write time must be extremely short
Solution Approach 1:
The retainer node circuit prepares and validates state information before the actual RRAM write operation. This preliminary preparation ensures that the write operation itself can be completed extremely quickly (under 50 nanoseconds) with minimal power consumption, as the data is already formatted and ready for transfer.
Solution Approach 2:
The patent replaces traditional mechanical or electronic switching mechanisms with resistive switching in RRAM. This substitution enables extremely fast write operations with low power consumption, as resistive switching occurs at the nanosecond scale without requiring continuous current flow during state retention.
4Loss of time
If volatile multi-state components remain active, then immediate state access is possible, but continuous power consumption prevents battery operation efficiency
Solution Approach 1:
The system performs preliminary state capture to non-volatile memory before entering sleep mode. Upon power-up, the retainer node circuit rapidly restores the state in under 50 nanoseconds, making the effective state access time negligible compared to the power savings achieved during extended sleep periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables rapid state retention and restoration with minimal power consumption, allowing electronic devices to perform wireless signaling without interruption and providing substantial power savings, especially for devices operating on battery power.
Implementation Method 1
exhibits electrical pulse induced hysteretic resistance switching effects
Implementation Method 2
resistive-switching memory cell
Implementation Method 3
a filament(s) can be formed between the electrodes by a diffusion or drift of ions
Implementation Method 4
a filament(s) can be formed between the electrodes by a diffusion or drift of ions
Data Source
AI summary
A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.