SRAM Write Assist Circuit Using Charge Sharing for Low Voltage
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Solution Overview
Problem
As semiconductor processes advance, ensuring the write capability of static random access memory (SRAM) becomes challenging due to the similarity in capabilities between pass-gate and pull-up transistors, leading to failure in write operations, especially at low voltages, with existing solutions like Negative Bit-Line and voltage decrease techniques facing issues of high power consumption and data locking problems.
Innovation Solution
The SRAM write assist device and method incorporate a power circuit, write driving circuit, charge sharing circuit, coupling-capacitor charging circuit, and negative voltage coupling circuit to manage power supply and voltage levels, using a charge sharing capacitor with smaller capacitance to reduce power consumption while ensuring effective write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitance of the charge sharing capacitor is increased to match parasitic capacitors, then the voltage of bit lines can be pulled down to a lower level, but the power consumption increases due to frequent charging and discharging
Solution Approach 1:
The charge sharing capacitor is pre-charged to a specific voltage level before the write operation. During the write process, this pre-charged capacitor is connected to the bit line to provide the necessary voltage drop, eliminating the need for a large capacitor that would require frequent full charging cycles, thus reducing power consumption while maintaining write capability
Solution Approach 2:
The invention changes the voltage parameter of the charge sharing capacitor dynamically - it is charged to different voltage levels depending on the write operation requirements. By adjusting the capacitor's voltage state rather than relying solely on capacitance magnitude, the system achieves effective bit line voltage control with reduced energy expenditure
2Reliability
If the power voltage for SRAM cells is decreased to reduce pull-up transistor current, then the write operation becomes easier, but the data locking capability of the SRAM cells is affected
Solution Approach 1:
The power supply to SRAM cells is segmented into different phases: during the write operation, power is reduced to facilitate voltage pulling down, while during the hold/retention phase, full power is restored to maintain data locking. This temporal segmentation of power supply allows both write ease and data stability to be achieved at different times
Solution Approach 2:
The power voltage to SRAM cells is made dynamic rather than static - it changes based on the operational phase. The system dynamically adjusts power levels to match the requirements of different operational states (write vs. hold), enabling the pull-up transistor current to be reduced during writes while maintaining full strength for data retention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient write assist functions with reduced power consumption and improved write capability by managing voltage levels and power supply effectively, addressing the limitations of prior art.
Implementation Method 1
couple the power-receiving terminal of the column of SRAM cells with a first terminal of a charge sharing capacitor included in the negative voltage coupling circuit, which consequently lowers the voltage at the power-receiving terminal of the column of SRAM cells by charge sharing between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor
Implementation Method 2
generate a negative voltage by capacitive coupling when the voltage of a bit line of an SRAM cell is pulled down to 0V in the late stage of a write cycle
Data Source
AI summary
An SRAM write assist device includes: a power circuit supplying power to an SRAM-cells column and then stopping supplying power to make the voltage of a power-receiving terminal of the SRAM-cells column floating; a write driving circuit coupling a bit line of the SRAM-cells column with a ground terminal according to a data signal in a write drive phase; a charge sharing circuit coupling the power-receiving terminal with the first terminal of a capacitor to lower this terminal's floating voltage by charge sharing in a charge sharing phase; a charging circuit including a switch turned on to charge the capacitor with an operating voltage in a charge phase; and a negative-voltage coupling circuit including the capacitor whose first and second terminals are coupled to a ground terminal and the bit line respectively to lower the voltage of the bit line by charge sharing in a negative-voltage generation phase.