Mixed 1T and MT Memory Cell Architecture for Row Hammer Mitigation
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Solution Overview
Problem
As memory components decrease in size, the increased density of memory cells leads to faster data degradation due to repeated access, known as a 'row hammer' attack, which complicates the auto refresh operation and requires additional time for tracking access counts, thereby degrading memory performance.
Innovation Solution
The implementation of mixed 1T and MT memory cell architectures within the same memory array, where MT cells are used for counter memory cells to store access counts, allowing for faster read-modify-write cycles and reduced access times, while maintaining compatibility with existing processes and minimizing layout changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to improve storage capacity, then memory capacity increases, but data degradation rate increases due to row hammer attacks
Solution Approach 1:
The memory array is divided into multiple banks, and each bank is further divided into segments with independent refresh control. This segmentation allows selective refreshing of only those segments affected by row hammer attacks, rather than refreshing the entire memory array, thus maintaining high density while mitigating data degradation in specific regions.
Solution Approach 2:
Different refresh strategies are applied to different regions of the memory array based on their access patterns and degradation levels. High-access regions receive more frequent refreshes while low-access regions use standard refresh intervals, optimizing reliability without sacrificing overall density or performance.
2Reliability
If access tracking circuitry is added to monitor row hammer attacks, then memory reliability improves, but access time increases due to additional write operations
Solution Approach 1:
Access counts are incremented in advance during each memory access operation, and refresh operations are scheduled based on pre-calculated thresholds. This preliminary tracking and pre-scheduling eliminates the need for additional write operations during normal access, reducing time loss while maintaining reliability.
Solution Approach 2:
The memory system performs self-monitoring of access patterns and automatically triggers refresh operations when thresholds are exceeded, without requiring external intervention or additional control circuitry that would increase access time. The system serves its own reliability needs through embedded tracking logic.
3Productivity
If separate fabrication processes are used for 1T and MT memory cells to optimize performance, then memory performance improves, but manufacturing complexity increases
Solution Approach 1:
A single fabrication process is designed to produce both 1T and MT memory cell structures using the same process steps and materials. The process utilizes standard CMOS technology with additional patterning steps to create the multi-transistor structures, eliminating the need for separate specialized processes while maintaining performance optimization for both cell types.
Solution Approach 2:
The memory array uses a composite architecture where 1T and MT cells are integrated within the same array using compatible materials and structures. Both cell types share common process steps including transistor formation, interconnect fabrication, and material deposition, allowing unified manufacturing while preserving the performance benefits of each cell type.
Data Source
AI summary
Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.