Delay Test Circuit for Semiconductor Integrated Circuits
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Solution Overview
Problem
Current techniques for at-speed delay testing of semiconductor integrated circuits face challenges in efficiently testing multi-cycle paths and inter-domain paths due to limitations in clock pulse generation and delay adjustment, leading to increased data processing requirements and impractical design restrictions.
Innovation Solution
A semiconductor integrated circuit with a delay test circuit that generates output clock pulses by removing optional pulses from an input clock signal, allowing for adjustable timing and waveform control of clock pulses, enabling effective at-speed delay testing of multi-cycle and inter-domain paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high operating rate LSI tester is used to carry out at-speed delay test, then the test accuracy is improved, but the test cost increases and manufacturing cost increases
Solution Approach 1:
The patent applies dynamics by making the clock signal generation flexible and adjustable within the semiconductor integrated circuit itself. The delay test circuit can dynamically generate clock pulses at the required operating rate without requiring an expensive high-rate LSI tester, thus maintaining test accuracy while reducing manufacturing cost.
Solution Approach 2:
The semiconductor integrated circuit performs self-testing by incorporating a delay test circuit that can generate its own clock signals for at-speed delay testing. This eliminates the need for external high-rate LSI testers, allowing the circuit to test itself at the required operating rate without increasing manufacturing cost.
2Ease of operation
If a PLL circuit is incorporated into the semiconductor integrated circuit to generate clock signal, then the ease of operation is improved, but the device complexity increases
Solution Approach 1:
The patent extracts the essential clock generation function from a complex PLL circuit and implements a simplified delay test circuit that generates only the specific clock pulses needed for at-speed delay testing. This reduces device complexity while maintaining ease of operation for testing purposes.
Solution Approach 2:
Instead of implementing a full PLL circuit with all its components, the patent uses a partial implementation that only generates the necessary clock pulses for delay testing. This partial action approach reduces device complexity while still providing the required functionality for at-speed delay testing.
3Adaptability or versatility
If conventional clock pulse generation technique is used for at-speed delay test, then the data processing requirement is reduced, but the adaptability for multi-cycle and inter-domain paths is limited
Solution Approach 1:
The delay test circuit is designed with multi-functionality to handle various testing scenarios including single-cycle paths, multi-cycle paths, and inter-domain paths. By generating clock pulses with adjustable timing and waveform characteristics, the same circuit can adapt to different test requirements without requiring separate specialized circuits for each path type.
Solution Approach 2:
The patent uses parameter changes by adjusting the timing and waveform characteristics of generated clock pulses to suit different testing scenarios. The delay test circuit can modify pulse generation parameters (timing, duration, frequency) to accommodate multi-cycle and inter-domain paths, providing adaptability without excessive data processing requirements.
Data Source
AI summary
A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies the output clock pulse to the input side flip-flop and the output side flip-flop.