Delayed-Reset Phase-Frequency Detector for Lower PLL In-Band Noise
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Solution Overview
Problem
Conventional phase-locked loop (PLL) circuits face challenges in reducing in-band phase noise floor, particularly due to high noise contributions from the phase-frequency detector (PFD) and charge pump (CP) block, where increasing charge pump current leads to increased power consumption and noise, while reducing it limits tuning range.
Innovation Solution
A modified PFD circuit design that introduces a time delay to the data signals used for resetting flip-flops, allowing both current sources to be active for small phase errors, thereby increasing gain without increasing charge pump current, and utilizing additional AND logic gates and delay elements to achieve a higher slope for phase errors less than a certain magnitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If charge pump current is increased to reduce in-band phase noise floor, then phase noise contribution is reduced, but power consumption increases and voltage headroom decreases
Solution Approach 1:
The patent changes the operational parameters of the charge pump by enabling both current sources to be active simultaneously for small phase errors, effectively doubling the charge pump current without increasing the maximum current capability. This achieves lower phase noise (improving the harmful factor) while maintaining the same power consumption and voltage headroom (avoiding the worsening effect)
Solution Approach 2:
The patent introduces dynamic control of the charge pump current sources based on the magnitude of phase error. For small phase errors, both current sources are activated to provide doubled current and reduced noise. For larger phase errors, only one current source is active. This dynamic adaptation allows the system to optimize noise performance without permanently increasing power consumption
2Power
If charge pump current is increased to increase gain, then gain is improved, but noise of charge pump increases
Solution Approach 1:
The patent changes the current parameter dynamically based on phase error magnitude. By activating both current sources only when phase error is small, the system achieves doubled gain (improving the power parameter) while avoiding the increased noise that would result from continuously high current operation (preventing the worsening of harmful factors)
3Use of energy by moving object
If charge pump current is reduced to decrease power consumption, then power consumption is reduced, but tuning range of VCO is limited
Solution Approach 1:
The patent implements dynamic current control where both current sources are activated only for small phase errors. This allows the system to maintain low average power consumption (improving the energy parameter) while providing high current availability when needed for wide VCO tuning range (preserving the adaptability parameter). The dynamic activation ensures that the full tuning range capability is available without continuously consuming high power
Data Source
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Figure 3A~3C
AI summary
Proposed is a phase-frequency detector, PFD, circuit suitable for use in a phase lock loop, PLL, circuit. The PFD circuit comprises: a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference; and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.