Continuous-Time Delta-Sigma ADC Feedback for Jitter-Tolerant Sampling
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Solution Overview
Problem
Continuous-time delta-sigma analog-to-digital converters (ADCs) face sensitivity issues due to clock jitter and loop delay, particularly in inner loops, and are sensitive to clock jitter and thermal noise in outer loops, affecting noise performance and power consumption.
Innovation Solution
The design incorporates two or more digital-to-analog converters (DACs) with pulsed feedback signals in separate feedback loops, where the first DAC in an inner loop generates a pulse proportional to the digital output sample with a duration between (n+α1)T and (n+β1)T, and the second DAC in an outer loop generates a pulse with a duration between (n+α2)T and (n+β2)T, optimizing noise performance and reducing sensitivity to delays and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single feedback DAC is used in conventional CT modulators, then the device complexity is low, but the sensitivity to clock jitter and loop delay increases
Solution Approach 1:
The feedback path is segmented into multiple parallel DACs (first feedback DAC and second feedback DAC) with different pulse width characteristics. This segmentation allows each DAC to handle specific aspects of the feedback signal, reducing the sensitivity to clock jitter and loop delay while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The system employs dynamic pulse width modulation where the first feedback DAC generates pulses with width between (n+α1)T and (n+β1)T, and the second feedback DAC generates pulses with width between (n+α2)T and (n+β2)T. This dynamic timing control optimizes noise performance and reduces jitter sensitivity by adaptively adjusting pulse characteristics based on operating conditions.
2Measurement precision
If the sampling rate is increased to improve noise performance, then the noise performance improves, but the power consumption increases
Solution Approach 1:
The invention changes the temporal parameters of the feedback pulses by controlling their widths to specific intervals ((n+α1)T to (n+β1)T for first DAC, (n+α2)T to (n+β2)T for second DAC). This parameter optimization allows achieving improved noise performance through better noise shaping without proportionally increasing power consumption, as the pulse width control optimizes the efficiency of each switching event.
3Reliability
If pulsed feedback signals with optimized timing are used, then the sensitivity to clock jitter and loop delay is reduced, but the device complexity increases
Solution Approach 1:
The system implements feedback mechanisms where the quantized analog signal is converted to digital form and fed back through multiple DACs with controlled pulse widths. This feedback loop continuously adjusts the pulse timing parameters (α1, β1, α2, β2) to maintain optimal performance, reducing sensitivity to clock jitter and loop delay through closed-loop control rather than requiring complex open-loop timing mechanisms.
Data Source
AI summary
A continuous-time ΔΣ-ADC (1) is disclosed, comprising a sampled quantizer (5) arranged to generate samples y(n) of a digital output signal of the ΔΣ-ADC (1) at sample instants nT. The ΔΣ-ADC (1) further comprises two or more DACs (10a-b), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (5), and a continuous-time analog network (20) arranged to generate an analog input signal to the quantizer (5) based on the feedback signal(s) from the two or more DACs (10a-b) and an analog input signal to the ΔΣ-ADC (1). At least a first DAC (10a) of the two or more DACs (10a-b) is adapted to generate a pulsed feedback signal that, for each n, comprises a pulse, the magnitude of which is proportional to the sample of the digital output signal at sample instant nT and which lasts between the time instants (n+a1)T and (η+β1)T, wherein 0<α1<β1<1. Aí least a second DAC (10b) of the two or more DACs (10a-b) is adapted to generate a pulsed feedback signal that, for each n, comprises a pulse, the magnitude of which is proportional to the sample of the digital output signal at sample instant nT and which lasts between the time instants (n+a2)T and (η+β2)T, wherein 0<a2<1<β2. The first DAC (10a) is located in a first feedback loop and the second DAC (10b) is located in a second feedback loop, which is an outer feedback loop relative to the first feedback loop. A corresponding radio receiver circuit, a corresponding integrated circuit, and a corresponding radio communication apparatus are also disclosed.