Analogue Conversion TRIZ Cases

Signal-amplitude-triggered shuffling cuts element mismatch distortion while limiting added noise during low-level signals.

Delayed digital outputs switch quantizer reference potentials to compensate excess loop delay with lower power than extra DACs and buffers.

Code conversion turns high-rate Σ-Δ speaker signals into lower-rate PWM, cutting switching loss, heating, and distortion across channels.

Dynamic gain switching across delta-sigma and cyclic stages improves AD converter linearity and prevents missing codes in compact sensors.

Multiple phase-shifted FDSMs disperse idle tone noise before summation, improving SNR and frequency measurement accuracy.

Reference-voltage calibration and arithmetic correction improve sensor output accuracy without large memory-hungry lookup tables.

A filtered digital correction path cancels first-stage feedback DAC mismatch in high-speed MASH ADCs and lifts SNDR without error transfer knowledge.

Multiple bandpass interpolation branches decompose high-frequency signals to cut sampling-jitter noise and preserve ADC precision near Nyquist.

Delta-sigma modulators give configurable processing devices flexible analog I/O with strong signal stability and cost-effective mixed-signal integration.

DAC unit elements measure each other's static mismatch in CT delta-sigma modulators, cutting harmonic distortion without extra circuitry.

Rotational dynamic element matching in a multi-bit DAC cuts mismatch-driven spectral noise and preserves linearity and SNR.

Leakage-blocking memory switches and op-amp reset cut settling time and channel cross-talk in multiplexed delta-sigma ADCs.

A dual-DAC transmitter shapes only narrow-bit signals at higher rate, cutting computation while creating noise-spectrum notches.

A third reference voltage with delta-sigma shuffling cuts DAC power use and flicker noise while preserving analog conversion precision.

A band-pass sigma-delta modulator shapes RF quantization noise so switch-mode power DACs can raise efficiency at high data rates.

Multi-stage gain and offset adjustment lets a 1-bit delta-sigma transmitter run fast while lowering quantization noise.

Adaptive conjugate filtering corrects frequency-dependent I/Q imbalance in quadrature receivers, cutting distortion and lowering the noise floor.

A programmable decimation filter adjusts clock values and coefficients per channel to remove noise across mixed bandwidths without complex anti-aliasing filters.

Multiple feedback gain paths stabilize sigma-delta modulation at high speed by balancing quantizer delay, gain, and meta stability.

Low-level input detection switches audio output to a constant signal, suppressing idle tones and audible noise without extra filters.

Multiple pulsed feedback DACs in inner and outer loops cut clock jitter and loop-delay sensitivity while improving ADC noise performance.

Quantization indices and adaptation parameters enable ADPCM audio processing without full decoding, cutting complexity and preserving signal quality.

Dynamic capacitor-group switching cuts ADC capacitive loading to preserve input range and reduce harmonic distortion and noise.

Limiting mixers, smoothing filters, and digital matrix filtering let parallel subconverters achieve high sampling rates with lower bandwidth and power.

Half-rate chopping in a continuous-time sigma-delta ADC enables direct high-frequency signal conversion while reducing mixer complexity and noise.

Multiple feedback paths with different gain values let a sigma-delta modulator run faster or at lower power while avoiding metastability.

Using lower- and higher-rate ADCs with sampling-rate interpolation, this case cuts power while preserving SNR across a wide dynamic range.

Phase-shifted interleaved DAC paths and reconfigurable delta-sigma modulators widen bandwidth while lowering noise and canceling images.

A differentiated quantization-error feedback path suppresses out-of-band noise near the oversampling frequency without adding DACs.

A split analogue-digital loop keeps sigma-delta ADCs stable across sample rates while lowering power, jitter sensitivity, and quantization noise.

A capacitive feedback DAC cuts first-opamp output swing in a continuous-time sigma-delta ADC while preserving transfer function and noise performance.

Pre-computed reference switching compensates excess loop delay in CTDSMs, enabling higher sampling rates with better stability and SNR.

Low-pass delta-sigma modulation and multiphase carrier switching cut average output frequency, easing GHz RF power device losses.

Variable impedance with delta-sigma control shifts RFID tags onto dedicated frequency channels, cutting collisions and improving read throughput.

Band-pass delta sigma control of coupled impedance creates dedicated RFID channels, cutting tag collisions, DC offset, and phase noise.

Selective decimation and interpolation extend LPCM output to common audio sample rates despite MEMS microphone clock limits.

A reservoir capacitor replaces resistive DAC references to cut power draw and noise floor while preserving high dynamic range.

External trigger capture records decimation counter and output values in a sigma-delta ADC, cutting DMA channel area without losing precision.

Step-size estimation corrects CVSD decoder state divergence after bursty bit errors, reducing lingering audio artifacts without re-encoding.

Envelope-based sub-band gain control improves duplex audio quality in portable CODECs while keeping processing resources efficient.

Alternate-bit summing and inverse comparison detects repetitive 8-bit silence patterns, helping prevent audio amplifier overload and artifacts.

A paired RC integrator topology cancels transfer-function terms to deliver high-order CTDS filtering with fewer op-amps, lower power, and smaller circuits.

Time-warping aligns decoded and extrapolated audio after lost frames, smoothing packet-loss transitions in sub-band predictive coders.

Counter-based digital detection replaces analog peak circuits to improve signal threshold accuracy while cutting power, offsets, and die area.

A common-mode adjust and tuning circuit keeps sigma-delta ADC inputs within the desired range, improving startup reliability and signal integrity.

Waveform extrapolation in separate sub-bands conceals lost G.722 ADPCM frames, preserving wideband audio quality and reducing artifacts.

After packet loss, decoded audio is time-warped to match an extrapolated frame, smoothing phase transition in sub-band ADPCM speech decoding.

A PDM feedback loop in a programmable mixed-signal chip generates an analog reference voltage without dedicated analog output pins.

A CIC decimator and ASRC resample oversampled low-IF or zero-IF receiver signals while avoiding a channelization filter to cut power and area.

Parallel bandpass branches with continuous-time noise shaping help ADCs combine wide instantaneous bandwidth with higher resolution.