Delta-Sigma Quantizer Reference Switching for Excess Loop Delay
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Solution Overview
Problem
Continuous time delta sigma modulators suffer from excess loop delay, which can be reduced but often increases power consumption, and existing solutions like adding additional DACs and delay buffers are not efficient in terms of power usage.
Innovation Solution
A reference module that adjusts reference potentials based on delayed digital outputs, using a switching module with resistors and a switch control module to vary the reference potentials, reducing quantizer delay without the need for additional power-consuming components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If additional DACs and delay buffers are added to reduce excess loop delay, then quantizer delay is reduced, but power consumption increases
Solution Approach 1:
The patent changes the reference potential parameters dynamically based on delayed digital outputs. By adjusting reference potentials rather than adding physical delay components, the system reduces quantizer delay without the power penalty of additional DACs and buffers.
Solution Approach 2:
The patent uses a buffer module to store and retrieve digital outputs, creating a time-delayed version of the digital signal. This copying approach achieves delay compensation without requiring additional power-consuming DACs and delay buffers in the main signal path.
2Speed
If the clock signal frequency is increased to reduce delay, then quantizer delay is reduced, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing delayed digital outputs in a buffer module before they are needed for reference potential adjustment. This allows the system to compensate for delay without increasing the clock frequency, thereby avoiding the power consumption associated with higher-speed operation.
3Loss of time
If a buffer module with delay less than one clock cycle is used, then excess loop delay is compensated, but device complexity increases
Solution Approach 1:
The patent merges the buffer module functionality with the existing quantizer and reference module. By integrating the delay buffer into the existing architecture and using it to control reference potential switching, the system compensates for excess loop delay without significantly increasing overall device complexity.
Data Source
AI summary
A continuous time delta sigma modulator includes a quantizer, a buffer module, and a reference module. The quantizer includes a comparator that updates a digital output each cycle of a clock signal based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module receives the digital output, stores the digital output for a predetermined delay period, and outputs the digital output after the predetermined delay period as a delayed digital output. The predetermined delay period is less than one cycle of the clock signal. The reference module selectively varies the reference potential based on the delayed digital output.