Adaptive Flash Converter Capacitance Reduction for Lower THD
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Solution Overview
Problem
Delta-sigma modulated analog-to-digital converters face challenges in balancing stable input voltage range and noise shaping, leading to increased total harmonic distortion and noise, especially when the input signal exceeds the stable range, causing unpredictable behavior and potential oscillation.
Innovation Solution
A capacitance reduction circuit that dynamically enables or disables switched capacitor summing circuits and dynamic comparators based on the most significant and least significant bits of the digital code, reducing capacitive loading and improving harmonic distortion and noise performance by selectively sampling the quantizing signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If severe noise shaping is applied in delta-sigma modulated ADC, then quantization noise in the frequency band of interest is attenuated, but the stable input range becomes limited and total harmonic distortion increases
Solution Approach 1:
The patent applies dynamics by making the capacitive load adaptive rather than fixed. The switched capacitor summing circuits are dynamically enabled or disabled based on the input signal amplitude detected by the capacitance reduction circuit. When the input signal exceeds a predetermined threshold, the capacitive load is reduced by disabling certain switched capacitor circuits, allowing the system to maintain stability at high input levels while preserving noise shaping performance at lower levels.
2Object-affected harmful factors
If severe noise shaping is applied in delta-sigma modulated ADC, then quantization noise in the frequency band of interest is attenuated, but total harmonic distortion and noise performance deteriorate when input signal exceeds stable range
Solution Approach 1:
The patent implements feedback through the capacitance reduction circuit that continuously monitors the input signal amplitude and adjusts the capacitive load accordingly. When the input signal amplitude exceeds a predetermined threshold, the feedback mechanism triggers the disabling of certain switched capacitor summing circuits, reducing the capacitive load and preventing excessive total harmonic distortion while maintaining the noise shaping benefits.
3Stability of the object's composition
If large capacitive load is used in summation-quantization circuits, then stable input range is maximized, but settling time increases and total harmonic distortion worsens
Solution Approach 1:
The patent applies dynamics by making the capacitive load adaptive rather than fixed. The switched capacitor summing circuits are dynamically enabled or disabled based on the input signal amplitude detected by the capacitance reduction circuit. When the input signal exceeds a predetermined threshold, the capacitive load is reduced by disabling certain switched capacitor circuits, allowing the system to maintain stability at high input levels while preserving noise shaping performance at lower levels.
Data Source
AI summary
A capacitance reduction circuit retains a conversion digital code of a previous sampling of an input signal of a delta-sigma modulated ADC and compares a set of least significant data bits and most significant bits of the conversion digital code to a least significant and a most significant boundary codes. When the least significant bits of the conversion digital code are less than or equal to the least significant boundary code or when the most significant bits of the conversion digital code are greater than or equal to the most significant boundary code, the capacitance reduction circuitry generates a capacitance reduction enable/disable code applied to multiple summation-quantization circuits to enable or disable groups of the multiple summation-quantization circuits bits to reduce capacitive loading of the outputs of delta-sigma modulator and an input signal to improve the total harmonic distortion and noise.