Digital Front End Using CIC and ASRC Without Channelization Filter
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Solution Overview
Problem
Existing digital radio receivers face challenges in power efficiency and area optimization, particularly in low-power applications such as portable digital radios, due to the need for complex filtering and clock synchronization.
Innovation Solution
The implementation of a cascaded integrated comb (CIC) decimation filter and an asynchronous sample rate converter (ASRC) in the digital front end, which allows for aliased artifacts to be kept below a threshold magnitude without a channelization filter, by carefully selecting the CIC filter response and ASRC resample rate, and the use of an oversampled delta sigma ADC to reduce noise and filter complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a channelization filter is used to remove undesired out-of-band signals, then signal quality is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent removes the channelization filter from the signal processing chain by exploiting the noise-shaping property of oversampled delta-sigma ADCs. The ADC inherently pushes quantization noise to frequencies outside the band of interest, eliminating the need for separate filtering hardware and reducing device complexity while maintaining signal quality.
Solution Approach 2:
The patent introduces an asynchronous sample rate converter (ASRC) as an intermediary component between the oversampled ADC and the baseband demodulator. The ASRC converts the oversampled signal to the appropriate baseband sampling rate while utilizing the already-filtered spectrum from the ADC, thereby avoiding the need for additional channelization filtering.
2Adaptability or versatility
If multiple voltage-controlled oscillators are used for mixer LO and ADC sampling clock, then clock synchronization flexibility is improved, but power consumption and area increase
Solution Approach 1:
The patent merges the functions of multiple voltage-controlled oscillators into a single ASRC unit. The ASRC simultaneously provides both the mixer local oscillator signal and the ADC sampling clock, eliminating the need for separate VCOs and reducing power consumption while maintaining the required clock synchronization flexibility through its programmable frequency synthesis capability.
Solution Approach 2:
The ASRC is designed as a universal clock generation unit that can generate multiple clock signals (mixer LO and ADC sampling clock) from a single input reference, providing multi-functionality that replaces multiple dedicated oscillators and reduces overall system power consumption.
3Reliability
If oversampled delta sigma ADC is used to reduce noise, then signal quality is improved, but device complexity increases
Solution Approach 1:
The patent changes the sampling rate parameter by using oversampling (sampling at a rate much higher than the Nyquist rate) combined with noise shaping in the delta-sigma ADC architecture. This parameter change moves quantization noise to higher frequencies where it can be easily removed, improving signal quality while the subsequent ASRC handles the rate conversion to avoid complex digital filtering.
Data Source
AI summary
A digital radio signal is processed by converting an analog signal to a digital signal, decimating the digital signal using a CIC filter and supplying the decimated digital signal directly to an asynchronous sample rate converter (ASRC). The decimated signal is resampled in the ASRC and the ASRC output is supplied directly to a droop compensation filter to compensate the output of the ASRC. By carefully choosing the response of the CIC filter and the resample rate of the ASRC, aliased artifacts in the pass band can be kept below a threshold magnitude without the need for a channelization filter.