Split-Branch Sigma-Delta ADC for Stable Variable Sample Rates
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Solution Overview
Problem
Existing sigma delta analogue to digital converters (ADCs) face challenges in maintaining stability and low power consumption across varying sample rates, particularly in applications requiring both high dynamic range and flexibility, such as voice and high-end audio processing, while being sensitive to clock jitter and limited by fixed loop filters.
Innovation Solution
The design incorporates a split forward branch with an analogue filter and digital components, including a multi-bit digital integrator and finite impulse response digital to analogue converters, along with a digital sigma delta modulator block, allowing for scalability and reduced analogue circuitry. This configuration includes intermediate feedback loops and multiple sigma delta modulator blocks of varying orders to manage sample rates and power consumption effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If existing sigma delta ADCs use fixed loop filters, then stability is maintained at specific sample rates, but adaptability to varying sample rates deteriorates
Solution Approach 1:
The patent implements a dynamic filter coefficient adjustment mechanism where the loop filter coefficients are modified based on the detected sample rate. The system transitions from static fixed coefficients to dynamic adaptive coefficients, allowing the filter to optimize its performance for different sampling frequencies while maintaining stability across varying operating conditions.
Solution Approach 2:
The invention changes the parameters of the loop filter by adjusting its coefficients according to the sample rate. Different sets of filter coefficients are applied depending on the operating sample rate, enabling the system to adapt its filtering characteristics to match the specific sampling conditions while preserving stability.
2Measurement precision
If existing sigma delta ADCs operate at high sample rates, then dynamic range is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the sample rate based on application requirements, allowing operation at lower sample rates when full dynamic range is not needed. This dynamic sampling rate control enables the ADC to reduce power consumption by operating at lower rates for less demanding applications while maintaining the capability to switch to higher rates when maximum dynamic range is required.
Solution Approach 2:
The invention modifies the sampling rate parameter to optimize the trade-off between dynamic range and power consumption. By allowing variable sample rates rather than operating at a fixed high rate, the system can achieve acceptable dynamic range at lower power consumption levels for many applications.
3Measurement precision
If existing sigma delta ADCs use complex loop filters, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent changes the parameters of relatively simple loop filter structures by adjusting their coefficients rather than using complex fixed-filter designs. This parameter-based adaptation allows the system to achieve high dynamic range performance with simpler analogue circuitry by optimizing the filter behavior through coefficient modification rather than structural complexity.
Data Source
AI summary
An analog to digital converter comprises an input terminal configured to receive an analog input signal and an output terminal configured to provide an output digital signal. The analog to digital converter also comprises a main summer having a summing input, a subtracting input and a summing output, wherein the summing input is connected to the input terminal; an analog filter having a filter input and a filter output, wherein the filter input is connected to the summing output; a quantizer having a quantizer input and a quantizer output, wherein the quantizer input is connected to the filter output; a digital integrator having a digital integrator input and a digital integrator output, wherein the digital integrator output is configured to provide a multi-bit output signal, the digital integrator input is connected to the quantizer output, and the digital integrator output is connected to the output terminal; and a main feedback digital to analog converter having a main feedback converter input and a main feedback converter output, wherein the main feedback converter input is connected to the digital integrator output, and the main feedback converter output is connected to the subtracting input of the main summer.