Sigma-Delta ADC Trigger Capture for Intermediate Value Sampling
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Solution Overview
Problem
Sigma-delta analog to digital converters (SD-ADCs) require significant chip area and cost for direct memory access (DMA) channels to calculate intermediate values, which is inefficient for periodic measurements with shorter intervals than the converter's sampling period.
Innovation Solution
A method using a sigma-delta analog to digital converter with a modulator, decimation filter, and decimator data output, where external trigger signals capture decimation counter and decimator data output values, reducing the need for multiple DMA channels by utilizing capture function elements and a single DMA channel for storing SD-ADC and timer values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple DMA channels are used to capture SD-ADC values and timer values for calculating intermediate values, then the accuracy and resolution of measurements are maintained, but the chip area and system complexity increase significantly
Solution Approach 1:
The patent combines the capture of SD-ADC values and timer values into a single DMA channel operation. Instead of using separate DMA channels for each data type, the system uses one DMA channel to capture both the converter output and timer values simultaneously, reducing the number of DMA channels from three to one and thereby reducing chip area while maintaining measurement precision
Solution Approach 2:
The single DMA channel is designed to perform multiple functions: capturing SD-ADC values, capturing timer values, and managing data transfer to memory. This multi-functional approach replaces the need for dedicated DMA channels for each function, reducing overall system complexity and chip area while preserving the ability to maintain accurate measurements
2Productivity
If three DMA channels are used to move data from different modules to memory, then data capture capability is sufficient, but the system complexity and cost increase due to requiring custom-made modules
Solution Approach 1:
The patent implements a universal DMA channel that can handle multiple data capture tasks sequentially and simultaneously. This single multi-functional channel replaces three specialized channels, enabling the system to use generic modules instead of custom-made ones, thereby reducing system complexity while maintaining adequate data capture capability
Solution Approach 2:
The system changes the operational parameters of the single DMA channel to accommodate multiple functions. By adjusting timing, trigger conditions, and data transfer parameters, the channel can efficiently capture both SD-ADC values and timer values without requiring separate dedicated channels, thus reducing complexity while preserving productivity
3Area of stationary object
If a single DMA channel is used to capture both SD-ADC and timer values, then chip area is reduced, but the timing synchronization between values may become more challenging
Solution Approach 1:
The system prepares and captures timer values in advance alongside SD-ADC values using the single DMA channel. By having the timer values ready and synchronized at the moment of capture, the system ensures accurate timing relationships are maintained without requiring complex post-processing or additional synchronization hardware, thus reducing chip area while preventing timing loss
Data Source
AI summary
Some embodiments relate to a method for use in a sigma-delta analog to digital converter, sigma-delta analog to digital converters and systems comprising sigma-delta analog to digital converters. In accordance with an aspect of the invention, there is provided a method for use in a sigma-delta analog to digital converter (SD-ADC) comprising a modulator, a decimation filter, a decimation counter, and a decimator data output, wherein the method comprises receiving an external trigger signal and capturing a value of the decimation counter and a value of the decimator data output upon receiving the external trigger signal.